Abstract
Program behaviors reveal that programs have different sources requirement at different phases, even at continuous clocks. It is not a reasonable way to run different programs on constant hardware resources. So sharing feasible degree of hardware may get more benefits for programs.
This paper proposes architecture to share function units between neighbor cores in CMP to improve chip performance. Function units are central units on the core, it take little area and is not the performance critical part of core, but improving function units’ utilization can improve other units’ efficiency and core performance. In our design, share priority guarantees the local thread would not be influenced by threads in neighbor cores. Share latency is resolved by early share decision made and direct data path. The evaluation shows that the proposal is good for function unit intensive program and can drive other units more efficient.
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References
Hammond, L., Basem, A.N., Olukotuna, K.: A Single-Chip Multiprocessor. Computer 30, 79–85 (1997)
Dean, M.T., Susan, J.E., Henry, M.L.: Simultaneous Multithreading Maximizing On-Chip Parallelism. In: Proceedings of the 22nd Annual Int. Sym. on Computer Arch., Santa Margherita Ligure (1995)
Venkata, K., Josep, T.: A Clustered Approach to Multithreaded Processors. In: Proceedings of the 12th International Parallel Processing Symposium (1998)
James, B., Gaudiot, J.: Area and System Clock Effects on SMT/CMP Processors. In: International Conference on Parallel Architectures and Compilation Techniques (2001)
Dolbeau, R., Seznec, A.: CASH: Revisiting hardware sharing in single-chip parallel processor. IRISA Report 1491 (2002)
Rakesh, K., Norman, P.J., Dean, M.T.: Conjoined-Core Chip Multiprocessing. In: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture (2004)
Timothy, S., Suleyman, S., Brad, C.: Phase tracking and prediction. In: Proceedings of the 30th annual international symposium on Computer architecture (2003)
Timothy, S., Erez, P., Greg, H., Suleyman, S., Brad, C.: Discovering and Exploiting Program Phases. IEEE Micro (2003)
Butts, J.A., Sohi, G.S.: Characterizing and predicting value degree of use. In: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture (2002)
Francis, T., Yale, N.P.: Achieving Out-of-Order Performance with Almost In-Order Complexity. In: Proceedings of the 35th International Symposium on Computer Architecture (2008)
Barroso, L.A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., Verghese, B.: Piranha: a scalable architecture based on single-chip multiprocessing. In: Proceedings of the 27th annual international symposium on Computer architecture (2000)
Engin, I., Meyrem, K., Nevin, K., Jose, F.M.: Core fusion: accommodating software diversity in chip multiprocessors. In: Proceedings of the 34th annual international symposium on Computer architecture (2007)
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Chen, T., Ma, J., Yuan, H., Liu, J., Jiang, G. (2010). Function Units Sharing between Neighbor Cores in CMP. In: Hsu, CH., Yang, L.T., Park, J.H., Yeo, SS. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2010. Lecture Notes in Computer Science, vol 6081. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-13119-6_12
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DOI: https://doi.org/10.1007/978-3-642-13119-6_12
Publisher Name: Springer, Berlin, Heidelberg
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