Abstract
this paper presents a new test-data compression technique that uses exactly four codewords and sparse storage for testing embedded cores. It provides significant reduction in test-data volume with no any complex algorithm. It aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. In addition, the decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Experimental results for ISCAS’89 benchmarks illustrate the flexibility and efficiency of the proposed technique.
This research is supported by National Natural Science Foundation of China (NSFC) under grant No. 60773207 and 60673085.
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Ling, Z., Ji-shun, K., zhi-qiang, Y. (2010). Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core. In: Hsu, CH., Yang, L.T., Park, J.H., Yeo, SS. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2010. Lecture Notes in Computer Science, vol 6082. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-13136-3_44
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DOI: https://doi.org/10.1007/978-3-642-13136-3_44
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