Abstract
A novel parallel memetic algorithm (MA) architecture for the design of vector quantizers is presented in this paper. The architecture contains a number of modules operating memetic optimization concurrently. Each module uses steady-state genetic algorithm (GA) for global search, and K-means algorithm for local refinement. A shift register based circuit for accelerating mutation and crossover operations for steady state GA operations is adopted in the design. A pipeline architecture for the hardware implementation of K-means algorithm is also used. The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement.
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References
Gersho, A., Gray, R.M.: Vector Quantization and Signal Compression. Kluwer, Norwood (1992)
Hauck, S., Dehon, A.: Reconfigurable Computing. Morgan Kaufmann, San Francisco (2008)
Hwang, W.J., Li, H.Y., Yeh, Y.J., Chan, K.F.: FPGA Implementation of Competitive Learning with Partial Distance Search in the Wavelet Domain. In: Kang, G.B. (ed.) Progress in Neurocomputing Research, ch. 8, pp. 203–221. NOVA Science Publisher (2008)
Li, H.Y., Hwang, W.J., Hsu, C.C., Hong, C.L.: Efficient K-Means VLSI Architecture for Vector Quantization. In: Salberg, A.-B., Hardeberg, J.Y., Jenssen, R. (eds.) SCIA 2009. LNCS, vol. 5575, pp. 440–449. Springer, Heidelberg (2009)
Nedjah, N., Mourelle, L.: Hardware Architecture for Genetic Algorithms. In: Ali, M., Esposito, F. (eds.) IEA/AIE 2005. LNCS (LNAI), vol. 3533, pp. 554–556. Springer, Heidelberg (2005)
NIOS II Processor Reference Handbook, Altera Corporation (2008), http://www.altera.com/literature/lit-nio2.jsp
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Yu, TY., Hwang, WJ., Chiang, TC. (2010). Fast Parallel Memetic Algorithm for Vector Quantization Based for Reconfigurable Hardware and Softcore Processor. In: Tan, Y., Shi, Y., Tan, K.C. (eds) Advances in Swarm Intelligence. ICSI 2010. Lecture Notes in Computer Science, vol 6145. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-13495-1_59
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DOI: https://doi.org/10.1007/978-3-642-13495-1_59
Publisher Name: Springer, Berlin, Heidelberg
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