Skip to main content

Hardware Implementation of the Exponent Based Computational Core for an Exchange-Correlation Potential Matrix Generation

  • Conference paper

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6067))

Abstract

This paper presents an FPGA implementation of a calculation module for a finite sum of the exponential products (orbital function). The module is composed of several specially designed floating-point modules which are, fully pipelined and optimized for high speed performance. The hardware implementation revealed significant speed-up for the finite sum of the exponential products calculation ranging from 2.5x to 20x in comparison to the CPU. The orbital function is a computationally critical part of the Hartree-Fock algorithm. The presented approach aims to increase the performance of the part of the quantum chemistry computational system by employing FPGA-based accelerator. Several issues are addressed such as an identification of proper code fragments, porting a part of the Hartree-Fock algorithm to FPGA, data precision adjustment and data transfer overheads. The authors’ intention was also to make hardware application of the orbital function universal and easily attachable to different systems.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Underwood, K.D., Hemmert, K.S., Ulmer, C.: Architectures and APIs: assessing requirements for delivering FPGA performance to applications. In: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC 2006, Tampa, Florida, November 11-17, p. 111. ACM, New York (2006)

    Chapter  Google Scholar 

  2. Silicon Graphics, Inc. Reconfigurable Application-Specific Computing User’s Guide, Ver. 005, SGI (January 2007)

    Google Scholar 

  3. Gothandaraman, A., Peterson, G., Warren, G., Hinde, R., Harrison, R.: FPGA acceleration of a quantum Monte Carlo application. Parallel Computing 34(4-5), 278–291 (2008)

    Article  Google Scholar 

  4. Gothandaraman, A., Warren, G.L., Peterson, G.D., Harrison, R.J.: Reconfigurable accelerator for quantum Monte Carlo simulations in N-body systems. In: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, SC 2006, Tampa, Florida, November 11-17, p. 177. ACM, New York (2006)

    Chapter  Google Scholar 

  5. Mazur, G., Makowski, M.: Development and Optimization of Computational Chemistry Algorithms. In: KDM 2008, Zakopane, Poland (March 2008)

    Google Scholar 

  6. Wielgosz, M., Jamro, E., Wiatr, K.: Highly Efficient Structure of 64-Bit Exponential Function Implemented in FPGAs. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds.) ARC 2008. LNCS, vol. 4943, pp. 274–279. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  7. Jamro, E., Wielgosz, M., Wiatr, K.: FPGA implementation of 64-bit exponential function for HPC. In: FPL Proceedings, FPL Netherlands, August 27-29 (2007)

    Google Scholar 

  8. Omondi, A.R.: Computer Arithmetic Systems. Prentice Hall, Cambridge (1994)

    MATH  Google Scholar 

  9. Xilinx Virtex-4 Family Overview, http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf

  10. Parhi, K.K., Chung, J.G., Lee, K.C., Cho, K.J.: Low-error fixed-width modified booth multiplier, US Patent: 957244

    Google Scholar 

  11. SGI Altix 4700, http://www.sgi.com/products/servers/altix/4000/

  12. Ramdas, T., Egan, G.K., Abramson, D., Baldridge, K.: Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations. In: Proceedings of the 4th International Conference on Computing Frontiers, CF 2007, Ischia, Italy, May 7-9, pp. 267–276. ACM, New York (2007)

    Chapter  Google Scholar 

  13. Kandaswamy, M., Kandemir, M., Choudhary, A., Bernholdt, D.: Optimization and Evaluation of Hartree-Fock Application’s I/O with PASSION. In: Proceedings of the ACM/IEEE Conference on Supercomputing (SC), November 1997, pp. 31–50 (1997)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Wielgosz, M., Jamro, E., Wiatr, K. (2010). Hardware Implementation of the Exponent Based Computational Core for an Exchange-Correlation Potential Matrix Generation. In: Wyrzykowski, R., Dongarra, J., Karczewski, K., Wasniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2009. Lecture Notes in Computer Science, vol 6067. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14390-8_13

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-14390-8_13

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-14389-2

  • Online ISBN: 978-3-642-14390-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics