Abstract
Timing optimization is one of the most significant problems in VLSI design because it determines performance of the designed circuit. Such optimization problems contain hundreds of thousands of variables therefore they may be classified as high performance computing problems. In this paper we present the results of our parallel implementation of two popular approaches to integrated circuit timing optimization. Both approaches are based on the analytical placement computational scheme. The first approach is iterative net-weighting placement. The second executes buffer insertion algorithm after the placement cycle. We analyze effectiveness of both approaches, discuss their drawbacks and suggest ways of improvement.
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Meyerov, I., Kamaev, A., Kornyakov, K., Zhivoderov, A. (2010). Comparative Analysis of Effectiveness of Two Timing-Driven Design Approaches. In: Hsu, CH., Malyshkin, V. (eds) Methods and Tools of Parallel Programming Multicomputers. MTPP 2010. Lecture Notes in Computer Science, vol 6083. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14822-4_31
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DOI: https://doi.org/10.1007/978-3-642-14822-4_31
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-14821-7
Online ISBN: 978-3-642-14822-4
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