Abstract
In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues are the ordering of test vectors and scan registers with the goal of reducing switching activity during test application and power consumption as a consequence of the ordering. The principles of developing an optimizing procedure with the aim of achieving a solution satisfying the required value of power consumption during power consumption are described here. A basic description of the methodology together with the functions needed to implement the procedures is provided. Experimental results are also discussed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Raghunathan, A., Jha, N.K., Dey, S.: High-Level Power Analysis and Optimization, p. 175. Kluwer Academic Publishers, Boston (1998) ISBN 0-7923-8073-8
Roy, K., Prasad, S.C.: Low-Power CMOS VLSI Circuit Design, p. 359. Wiley-Interscience publication, Hoboken (2000) ISBN 0-471-11488-X
Nicolici, N., Al-Hashimi, B.M.: Power-Constrained Testing of VLSI Circuits, p. 178. Kluwer Academic Publishers, Dordrecht (2003) ISBN 1-4020-7235-X
Debjyoti, G., Swarup, B., Kaushik, R.: Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST. In: 18th IEEE International Symposium on De-fect and Fault Tolerance in VLSI Systems, pp. 191–198 (2003)
Dabholkar, V., Chakravarty, S., Pomeranz, I., et al.: Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application. IEEE Trans. on Computer-Aided Design of Integrated Circuits 17(12), 1325–1333 (1998)
Chakravarty, S., Dabholkar, V.: Minimizing Power Dissipation in Scan Circuits During Test Application. In: Proceedings of International Workshop on Low-Power Design (1994)
Pangrle, B., Kapoor, S.: Leakage power at 90nm and below [on-line]. EE Times Asia (2005), http://www.eetasia.com/ARTICLES/2005JUN/B/2005JUN01_POW_EDA_TA.pdf
Thompson, S., Packan, P., Bohr, M.: MOS Scaling: Transistor Challenges for the 21st Century. Intel Technology Journal 19 (1998)
Marongiu, A., et al.: Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology. In: Proceedings of the 11th Euromicro Conference on Digital System Designing Architectures, Methods and Tools, pp. 259–266 (2008)
Vranken, H., Waayers, T., Fleury, H., Lelouvier, D.: Enhanced Reduced-Pin-Count Test For Full-Scan Design. In: Proceedings of IEEE International Test Conference, pp. 738–747 (2001)
Almukhaizim, S., Makris., Y., Yang, Y.-S., Veneris, A.: Seamless Integration of SER in Rewiring-Based Design Space Exploration. In: Proceedings of International Test Conference, pp. 1–9 (2006)
Babighian, P., Kamhi, G., Vardi, M.: PowerQuest: Trace Driven Data Mining for Power Optimization. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition, pp. 1–6 (2007)
Girard, P., Landrault, C., Pravossoudovitch, S.: Reducing Power Consumption During Test Application by Test Vector Ordering. In: Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 296–299. IEEE Computer Society, Los Alamitos (1998)
Jelodar, M.S., Aavani, A.: Reducing Scan Base Testing Power Using Genetic Algorithm. In: Proc. of 11th Iranian Computer Engineering Conference, vol. 2, pp. 308–312 (2006)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Skarvada, J., Kotasek, Z., Strnadel, J. (2010). The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. In: Tempesti, G., Tyrrell, A.M., Miller, J.F. (eds) Evolvable Systems: From Biology to Hardware. ICES 2010. Lecture Notes in Computer Science, vol 6274. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15323-5_16
Download citation
DOI: https://doi.org/10.1007/978-3-642-15323-5_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15322-8
Online ISBN: 978-3-642-15323-5
eBook Packages: Computer ScienceComputer Science (R0)