Abstract
With the trend to integrate a large number of cores on a single chip, Network-on-Chips (NoCs) are becoming more important for communication on System-on-Chips (SoCs). Designing high throughput and low latency on-chip networks with reasonable area overhead is one of the main technical challenges. This paper proposes an architecture of router with on-the-fly virtual channel (VC) allocation for high performance on-chip networks. By performing the VC allocation during the time a packet is traversing the crossbar switch, the pipeline of a packet transfer can be shortened in a non-speculative fashion without the penalty of area. The proposed architecture has been implemented on FPGA and evaluated in terms of network latency, throughput and area overhead. The experimental results show that, the proposed router with on-the-fly VC allocation can reduce the network latency by 40.9%, and improve throughput by 47.6% as compared to the conventional VC router. In comparison with the look-ahead speculative router, it improves the throughput by 8.8% with 16.7% reduction of area for control logic.
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References
Benini, L., De Micheli, G.: Networks on Chips: A New SoC Paradigm. IEEE Computer 35, 70–78 (2002)
Owens, J.D., Dally, W.J., Ho, R., Jayasimha, D.N., Keckler, S.W.: Peh, Li-S. Research Challenges for On-Chip Interconnection Networks. IEEE Micro 27(5), 96–108 (2007)
Dally, W.J., Towles, B.: Route Packets, Not Wires: On-Chip Interconnection Networks. In: 38th Design Automation Conference, pp. 684–689 (2001)
Bjerregaard, T., Mahadevan, S.: A Survey of Research and Practices of Network-on-Chip. ACM Computing Surveys 38(1), 1–51 (2006)
Peh, L.-S., Dally, W.J.: A Delay Model and Speculative Architecture for Pipelined Routers. In: 7th International Symposium on High-Performance Computer Architecture, pp. 255–266 (2001)
Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2004)
Kim, J., Park, D., Theocharides, T., Vijaykrishnan, N., Das, C.R.: A Low Latency Router Supporting Adaptivity for On-chip Interconnects. In: 42nd Design Automation Conference, pp. 559–564 (2005)
Kim, J., Nicopoulos, C., Park, D., Narayanan, V., Yousif, M.S., Das, C.R.: A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks. In: International Symposium on Computer Architecture, pp. 4–15 (2006)
Mullins, R., West, A., Moore, S.: Low-Latency Virtual-Channel Routers for On-Chip Networks. In: 31st International Symposium on Computer Architecture, pp. 188–197 (2004)
Mullins, R., West, A., Moore, S.: The Design and Implementation of a Low Latency On-Chip Network. In: Asia and South Pacific Design Automation Conference, pp. 164–169 (2006)
Bertozzi, D., Benini, L.: Xpipes: A Network-on-Chip architecture for Gigascale Systems-on-Chip. IEEE Circuits and Systems Magazine, 18–31,Q.2 (2004)
Kumar, A.: Peh, Li-S., Kundu, P., Jha, N. K.: Express Virtual Channels: Towards the Ideal Interconnection Fabric. In: International Symposium on Computer Architecture, pp. 150–161 (2007)
Park, D., Das, R., Nicopoulos, C., Kim, J., Vijaykrishnan, N., Iyer, R., Das, C.R.: Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. In: IEEE Symposium on High-Performance Interconnects, pp. 15–20 (2007)
Michelogiannakis, G., Pnevmatikatos, D.N., Katevenis, M.: Approaching Ideal NoC Latency with Pre-Configured Routes. In: International Symposium on Networks-on-Chip, pp. 153–162 (2007)
Matsutani, H., Koibuchi, M., Amano, H., Yoshinaga, T.: Prediction Router: Yet Another Low Latency On-Chip Router Architecture. In: IEEE International Symposium on High-Performance Computer Architecture, pp. 367–378 (2009)
Kumar, A., Kundu, P., Singh, A.P.: Peh, Li-S., Jha, N. K.: A 4.6 Tbits/s 3.6 GHz Single-cycle NoC Router with a Novel Switch Allocation in 65nm CMOS. In: 25th International Conference on Computer Design, pp. 63–70 (2007)
Kim, J.: Low-cost Router Microarchitecture for On-chip Networks. In: 42nd IEEE/ACM International Symposium on Microarchitecture, pp. 255–266 (2009)
McKeown, N., Anantharam, V., Walrand, J.: Achieving 100% Throughput in an Input-Queued Switch. IEEE Transactions on Communications 47(8), 1260–1267 (1999)
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Nguyen, S.T., Oyanagi, S. (2011). An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel Allocation. In: Berekovic, M., Fornaciari, W., Brinkschulte, U., Silvano, C. (eds) Architecture of Computing Systems - ARCS 2011. ARCS 2011. Lecture Notes in Computer Science, vol 6566. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19137-4_19
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DOI: https://doi.org/10.1007/978-3-642-19137-4_19
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