Skip to main content

A Compact Gaussian Random Number Generator for Small Word Lengths

  • Conference paper
  • 1388 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6578))

Abstract

The architecture for a compact Gaussian Random Number Generator based on the inversion of the gaussian cdf for word lengths less than 8 bits is discussed. The generator occupies < 10% of area of conventional 16 or 32 bit GRNG implementations and thus can be useful in cases where a gaussian random number of small word length will suffice and area is at a premium.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Lee, D., Cheung, R., Villasenor, J., Luk, W.: Inversion-Based Hardware Gaussian Random Number Generator: a Case Study of Function Evaluation via Hierarchical Segmentation. In: IEEE International Conference on Field-Programmable Technology, pp. 33–40 (2006)

    Google Scholar 

  2. Zhang, G., Leong, P., Lee, D., Villasenor, J., Cheung, R., Luk, W.: Ziggurat Based Hardware Gaussian Random Number Generator. In: IEEE International Conference on Field-Programmable Logic and its Applications, pp. 275–280 (2005)

    Google Scholar 

  3. Zarubica, R., Wilson, S.G., Hall, E.: Multi-Gbps FPGA-Based Low Density Parity Check(LDPC) Decoder Design. In: IEEE Globecom, pp. 548–552 (2007)

    Google Scholar 

  4. Darabiha, A., Carusone, A., Kschischang, F.: A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC Decoder in 0.13-μm CMOS. In: Custom Integrated Circuits Conference, pp. 459–462 (2007)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Das, S., Patkar, S. (2011). A Compact Gaussian Random Number Generator for Small Word Lengths. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_10

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-19475-7_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-19474-0

  • Online ISBN: 978-3-642-19475-7

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics