Abstract
Coarse Grain Reconfigurable Architectures(CGRA) support Spatial and Temporal computation to speedup execution and reduce reconfiguration time. Thus compilation involves partitioning instructions spatially and scheduling them temporally. We extend Edge-Betweenness Centrality scheme, originally used for detecting community structures in social and biological networks, for partitioning instructions of a dataflow graph. Comparisons of execution time for several applications run on a simulator for REDEFINE, a CGRA proposed in literature, indicate that Centrality scheme outperforms several other schemes with 2–18% execution time speedup.
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Krishnamoorthy, R., Varadarajan, K., Fujita, M., Alle, M., Nandy, S.K., Narayan, R. (2011). Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_15
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DOI: https://doi.org/10.1007/978-3-642-19475-7_15
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