Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers

Abstract

Applications such as electrical power grid operation and planning rely on high-performance linear solvers involving large sparse matrices. Previous custom sparse solver hardware implemented on a Field Programmable Gate Array (FPGA) has shown an 8-fold performance gain over state-of-the-art sparse software packages. Generally, the drawback of hardware solvers lies in their design complexity. This paper presents an alternative architecture in which the host CPU software computes the main program and caches data that are streamed to a pipelined hardware, implemented on an FPGA, for part of the computation. With the lower-upper triangular decomposition solver, the hardware computes the sparse matrix row addition operation, called merging. The prototype merge core processes data at the optimum rate, i.e., the FPGA clock frequency. With the proposed triple-buffer bus architecture, the core is projected to attain a data rate of 250 MHz on the Virtex 6 FPGA in comparison to the average 200MHz for the merge software subroutine on a general-purpose processor.