Abstract
The large number of available DSP slices on new-generation FPGAs allows for efficient mapping and acceleration of floating-point intensive codes. Numerous scientific codes heavily rely on executing the exponential function. To this end, we present the design and implementation of a pipelined CORDIC/TD-based (COrdinate Rotation DIgital Computer/Table Driven) Exponential Approximation Unit (EAU) that will be made freely available for download (including the hardware description). The EAU supports single and double precision arithmetics and we provide appropriate configurations for Virtex2, Virtex4, and Virtex5 FPGAs. The architecture has been verified via simulations and by testing on a real FPGA. The implementation achieves the highest clock frequency reported in literature to date. Moreover, the EAU only occupies 5% of hardware resources on a medium-size FPGA such as the Virtex 5 SX95T. In addition, a general framework for safely conducting application-specific optimizations of floating-point operators on FPGAs is presented. We apply this framework to a bioinformatics application and optimize the EAU architecture using width-reduced floating-point operators and application-specific performance tuning. The optimized application-specific EAU occupies approximately 70% less hardware resources than the initial single precision implementation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Alachiotis, N., Sotiriades, E., Dollas, A., Stamatakis, A.: Exploring FPGAs for Accelerating the Phylogenetic Likelihood Function. In: Proceedings of HICOMB 2009, Rome, Italy, pp. 1–8 (2009)
Alachiotis, N., Stamatakis, A., Sotiriades, E., Dollas, A.: A Reconfigurable Architecture for the Phylogenetic Likelihood Function. In: Proceedings of FPL 2009, Prague, pp. 674–678 (September 2009)
Stamatakis, A.: RAxML-VI-HPC: maximum likelihood-based phylogenetic analyses with thousands of taxa and mixed models. Bioinformatics 22(21), 2688–2690 (2006)
Pottathuparambil, R., Sass, R.: A Parallel/Vectorized Double-Precision Exponential Core to Accelerate Computational Science Applications. In: Proceedings of FPGA 2009, Monterey, California, USA, pp. 285–285 (2009)
Pottathuparambil, R., Sass, R.: Implementation of a CORDIC-based Double-Precision Exponential Core on an FPGA. In: Proceedings of RSSI 2008, Urbana, Illinois, USA (2008)
Jamro, E., Wiatr, K., Wielgosz, M.: FPGA Implementation of 64-bit Exponential Function for HPC. In: Proceedings of FPL 2007, pp. 718–721 (2007)
Wielgosz, M., Jamro, E., Wiatr, K.: Highly Efficient Structure of 64-bit Exponential Function Implemented in FPGAs. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds.) ARC 2008. LNCS, vol. 4943, pp. 274–279. Springer, Heidelberg (2008)
Doss, C.C., Robert, J., Riley, L.: FPGA-based Implementation of a Robust IEEE-754 Exponential Unit. In: Proceedings of FCCM 2004, pp. 229–238 (2004)
de Dinechin, F., Klein, C., Pasca, B.: Generating High-Performance Custom Floating-Point Pipelines. In: Proceedings of FPL 2009, Prague (2009)
Detrey, J., de Dinechin, F.: Parameterized Floating-Point Logarithm and Exponential Functions for FPGAs. In: Proceedings of Microprocess. Microsyst., pp. 537–545 (2007)
Alachiotis, N., Stamatakis, A.: Efficient Floating-Point Logarithm Unit for FPGAs. In: Proceedings of RAW 2010, Atlanta, GA, USA, pp. 1–8 (2010)
Volder, J.E.: The CORDIC trigonometric computing technique. Proceedings of IRE Transactions on Electronic Computers, 330–334 (1959)
Walther, J.S.: A Unified Algorithm for Elementary Functions. In: Spring Joint Computer Conference, pp. 379–385 (1971)
Burkardt, J.: CORDCIC Approximation of Elementary Functions, http://people.sc.fsu.edu/~burkardt/cpp_src/cordic/cordic.html (last visited: 17-05-2010)
Xilinx: Floating Point Operator v.4.0, http://www.xilinx.com/support/documentation/ip_documentation/floating_point_ds335.pdf (last visited: 17-05-2010)
Boudabous, A., Ghozzi, F., Kharrat, M., Masmoudi, N.: Implementation of Hyperbolic Functions using CORDIC Algorithm. In: Proceedings of ICM 2001, pp. 738–741 (2004)
McGrath, R.: GNU C Library, http://www.gnu.org/software/libc (last visited: 17-05-2010)
Goldberg, D.: What every computer scientist should know about floating-point arithmetic. ACM Comput. Surv., 5–48 (1991)
Intel: Intel Math Kernel Library Reference Manual, http://www.intel.com/software/products/mkl/docs/WebHelp/mkl.htm
Goldman, N., Anderson, J.P., Rodrigo, A.G.: Likelihood-based tests of topologies in phylogenetics. Systematic Biology 49(4), 652–670 (2000)
Shimodaira, H., Hasegawa, M.: CONSEL: for assessing the confidence of phylogenetic tree selection. Bioinformatics 17(12), 1246 (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Alachiotis, N., Stamatakis, A. (2011). FPGA Optimizations for a Pipelined Floating-Point Exponential Unit. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_34
Download citation
DOI: https://doi.org/10.1007/978-3-642-19475-7_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19474-0
Online ISBN: 978-3-642-19475-7
eBook Packages: Computer ScienceComputer Science (R0)