Abstract
This paper describes a fault-tolerant scheduler that uses the Area-Time response Balancing algorithm (ATB) for scheduling real-time hardware tasks onto partially reconfigurable FPGAs. The architecture of the ATB scheduler incorporates fault-tolerance by design features; including Triple Modular Redundancy (TMR), parity protection of its memories and finite state machines, as well as spatial and implementation diversity. Additionally, it is able to scrub soft-errors and circumvent the permanent damage in the device. Besides the scheduling circuit is itself fault-tolerant, ATB is aware of the occurring faults in the silicon substrate of the chip, leading to a very reliable “fault-tolerant square scheduling”.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Constantinescu, C.: Trends and Challenges in VLSI Circuit Reliability. IEEE Micro Journal 23(4), 14–19 (2003)
Berg, M., Poivey, C., Petrick, D., Espinosa, D., Lesea, A., Label, K., Friendlich, M.: Effectiveness of Internal versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis. IEEE Transactions on Nuclear Science 55(4) (2008)
Montminy, D.P., Baldwin, R.O., Williams, P.D., Mullins, B.E.: Using Relocatable Bitstreams for Fault Tolerance. In: The Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, pp. 701–708 (2007)
Iturbe, X., Benkrid, K., Erdogan, A.T., Arslan, T., Azkarate, M., Martinez, I., Perez, A.: R3TOS: A Reliable Reconfigurable Real-Time Operating System. In: The Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, pp. 99–104 (2010)
Lu, Y., Marconi, T., Bertels, K., Gaydadjiev, G.: Online Task Scheduling for the FPGA-based Partially Reconfigurable Systems. In: The Proceedings of the Reconfigurable Computing: Architectures (2009)
Dittmann, F., Frank, S.: Hard Real-Time Reconfiguration Port Scheduling. In: The Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (2007)
Danne, K., Muehlenbernd, R., Platzner, M.: Executing Hardware Tasks on Dynamically Reconfigurable Devices under Real-time Conditions. In: Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 541–546 (2006)
Iturbe, X., Benkrid, K., Arslan, T., Martinez, I., Azkarate, M.: ATB: Area-Time Response Balancing Algorithm for Scheduling Real-Time Hardware Tasks. In: The Proceedings of the International Conference on Field-Programmable Technology (2010)
Liu, M., Kuehn, W., Lu, Z., Jantsch, A.: Run-Time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration. In: The Proceedings of the International Conference on Field Programmable Logic and Applications (2009)
NASA: Fault-Tolerant Coding for State Machines. NASA Tech Briefs NPO-41050 (2009)
Iturbe, X., Azkarate, M., Martinez, I., Perez, J., Astarloa, A.: A Novel SEU, MBU and SHE Handling Strategy for Xilinx Virtex-4 FPGAs. In: The Proceedings of the International Conference on Field Programmable Logic and Applications (2009)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Iturbe, X., Benkrid, K., Arslan, T., Azkarate, M., Martinez, I. (2011). A (Fault-Tolerant)2 Scheduler for Real-Time HW Tasks. In: Koch, A., Krishnamurthy, R., McAllister, J., Woods, R., El-Ghazawi, T. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2011. Lecture Notes in Computer Science, vol 6578. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19475-7_9
Download citation
DOI: https://doi.org/10.1007/978-3-642-19475-7_9
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19474-0
Online ISBN: 978-3-642-19475-7
eBook Packages: Computer ScienceComputer Science (R0)