Abstract
This paper describes a Fault Tolerance System (FTS) implemented in a new self-adaptive hardware architecture. This architecture is based on an array of cells that implements in a distributed way self-adaptive capabilities. The cell includes a configurable multiprocessor, so it can have between one and four processors working in parallel, with a programmable configuration mode that allows selecting the size of program and data memories. The self-elimination and self-replication capabilities of cell(s) are performed when the FTS detects a failure in any of the processors that include it, so that this cell(s) will be self-discarded for future implementations. Other self-adaptive capabilities of the system are self-routing, self-placement and runtime self-configuration.
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Soto, J., Moreno, J.M., Cabestany, J. (2011). Description of a Fault Tolerance System Implemented in a Hardware Architecture with Self-adaptive Capabilities. In: Cabestany, J., Rojas, I., Joya, G. (eds) Advances in Computational Intelligence. IWANN 2011. Lecture Notes in Computer Science, vol 6692. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21498-1_70
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DOI: https://doi.org/10.1007/978-3-642-21498-1_70
Publisher Name: Springer, Berlin, Heidelberg
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