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International Workshop on System Analysis and Modeling

SAM 2010: System Analysis and Modeling: About Models pp 72–90Cite as

Design and Development of a CPU Scheduler Simulator for Educational Purposes Using SDL

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Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6598))

Abstract

This paper presents the design and development of a CPU scheduler simulator using SDL. This simulator enables us to study the behavior of one level and multilevel queue scheduling algorithms (including the real-time ones), and to obtain performance statistics for algorithm evaluation. In addition, a multi-platform graphical user interface, based on the Tcl/Tk language, has been developed to simplify the simulator use. The paper also presents our experiences in using SDL for the specification of CPU scheduling algorithms for educational purposes.

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References

  1. Tcl Developer Xchange, http://www.tcl.tk

  2. Burns, A., Wellings, A.: Real-Time Systems and Programming Languages. Addison-Wesley, Reading (2002)

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  4. IBM: Telelogic SDL Suite 6.3 User’s Manual (September 2009)

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  6. International Telecommunication Union: Recommendation Z.100, Specification and Description Language (SDL) (November 2007), http://www.itu.int/rec/T-REC-Z.100/en

  7. Ontko, R.: MOSS Scheduling Simulator User Guide (May 2001), http://www.ontko.com/moss/sched/user_guide.html

  8. Robbins, S.: Using the Process Scheduling Simulator (January 2007), http://vip.cs.utsa.edu/simulators/guides/ps/ps_doc.html

  9. Silberschatz, A., Galvin, P.B., Gagne, G.: Operating System Concepts. John Wiley & Sons, Chichester (2005)

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  10. Stallings, W.: Operating Systems: Internals and Design Principles. Prentice-Hall, Englewood Cliffs (2005)

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  12. Tang, J.: Taccle: Tcl LALR Parser Generator (July 2008), http://wiki.tcl.tk/11425

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  14. Weller, J.: CPU Scheduler Application. University of Alaska Anchorage (March 2006), http://jimweller.com/jim-weller/jim/java_proc_sched

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Author information

Authors and Affiliations

  1. Department of Signal Theory and Telematics Engineering, University of Valladolid, ES-47011, Valladolid, Spain

    Manuel Rodríguez-Cayetano

Authors
  1. Manuel Rodríguez-Cayetano
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Editor information

Editors and Affiliations

  1. Department of Telematics, Norwegian University of Science and Technology (NTNU), Trondheim, Norway

    Frank Alexander Kraemer  & Peter Herrmann  & 

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© 2011 Springer-Verlag Berlin Heidelberg

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Rodríguez-Cayetano, M. (2011). Design and Development of a CPU Scheduler Simulator for Educational Purposes Using SDL. In: Kraemer, F.A., Herrmann, P. (eds) System Analysis and Modeling: About Models. SAM 2010. Lecture Notes in Computer Science, vol 6598. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21652-7_5

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  • DOI: https://doi.org/10.1007/978-3-642-21652-7_5

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-21651-0

  • Online ISBN: 978-3-642-21652-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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