Abstract
If current trends continue, today’s small-scale general-purpose CMPs will soon be replaced by multi-core architectures integrating tens or even hundreds of cores on-chip. Most likely, some of these many-core CMPs will implement the hardware-managed, implicitly-addressed, coherent caches memory model. Cache coherence in these designs will be probably maintained through a directory-based cache coherence protocol implemented in hardware. The organization of the directory structure will be a key design point due to the requirements in area that it will pose. In this work, we study the effects on performance, network traffic and area that the use of compressed sharing codes for the directory will have in many-core CMPs. In particular, we select two compressed sharing codes previously proposed in the context of large-scale shared-memory multiprocessors that have very small area requirements. Simulation results of 32-core CMPs show that degradations of up to 32% in performance and 350% in network traffic are experienced. Additionally, since some proposals for efficient multicast support in on-chip networks have recently appeared, we also consider the case of using this support in combination with the compressed sharing codes. Unfortunately, we found that multicast support is not enough to remove all the performance degradation introduced by the compressed sharing codes and barely can reduce network traffic.
We would like to thank anonymous reviewers for their suggestions. This research was supported by the Spanish MEC and MICINN, as well as European Commission FEDER funds, under Grants CSD2006-00046 and TIN2009-14475-C04, and PROMETEO from Generalitat Valenciana (GVA) under Grant PROMETEO/2008/060.
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References
Borkar, S.: Thousand core chips: A technology perspective. In: 44th Annual Design Automation Conference, pp. 746–749 (2007)
Taylor, M.B., Kim, J., Miller, J., et al.: The raw microprocessor: A computational fabric for software circuits and general purpose programs. IEEE Micro 22, 25–35 (2002)
Zhang, M., Asanović, K.: Victim replication: Maximizing capacity while hiding wire delay in tiled chip multiprocessors. In: 32nd Int’l Symp. on Computer Architecture (ISCA), pp. 336–345 (2005)
Intel Res.: Single-chip Cloud Computer (2010), http://techresearch.intel.com/articles/Tera-Scale/1826.htm
Leverich, J., Arakida, H., Solomatnikov, A., Firoozshahian, A., Horowitz, M., Kozyrakis, C.: Comparing memory systems for chip multiprocessors. In: 34th Int’l Symp. on Computer Architecture (ISCA), pp. 358–368 (2007)
Acacio, M.E., González, J., García, J.M., Duato, J.: A new scalable directory architecture for large-scale multiprocessors. In: 7th Int’l Symp. on High-Performance Computer Architecture (HPCA), pp. 97–106 (2001)
Rodrigo, S., Flich, J., Duato, J., Hummel, M.: Efficient unicast and multicast support for CMPs. In: 41st IEEE/ACM Int’l Symp. on Microarchitecture (MICRO), pp. 364–375 (2008)
Kim, C., Burger, D., Keckler, S.W.: An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. In: 10th Int. Conf. on Architectural Support for Programming Language and Operating Systems (ASPLOS), pp. 211–222 (2002)
Magnusson, P.S., Christensson, M., Eskilson, J., et al.: Simics: A full system simulation platform. IEEE Computer 35, 50–58 (2002)
Martin, M.M., Sorin, D.J., Beckmann, B.M., et al.: Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News 33, 92–99 (2005)
Puente, V., Gregorio, J.A., Beivide, R.: SICOSYS: An integrated framework for studying interconnection network in multiprocessor systems. In: 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, pp. 15–22 (2002)
Thoziyoor, S., Muralimanohar, N., Ahn, J.H., Jouppi, N.P.: CACTI 5.1. Technical Report HPL-2008-20, HP Labs (2008)
Horel, T., Lauterbach, G.: UltraSPARC-III: Designing third-generation 64-bit performance. IEEE Micro 19, 73–85 (1999)
Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: Characterization and methodological considerations. In: 22nd Int’l Symp. on Computer Architecture (ISCA), pp. 24–36 (1995)
Li, M.L., Sasanka, R., Adve, S.V., Chen, Y.K., Debes, E.: The ALPBench benchmark suite for complex multimedia applications. In: Int’l Symp. on Workload Characterization, pp. 34–45 (2005)
Wang, H., Peh, L.S., Malik, S.: Power-driven design of router microarchitectures in on-chip networks. In: 36th IEEE/ACM Int’l Symp. on Microarchitecture (MICRO), pp. 105–111 (2003)
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Ros, A., Acacio, M.E. (2011). Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. In: Guarracino, M.R., et al. Euro-Par 2010 Parallel Processing Workshops. Euro-Par 2010. Lecture Notes in Computer Science, vol 6586. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21878-1_12
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DOI: https://doi.org/10.1007/978-3-642-21878-1_12
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