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MyUT: Design and Implementation of Efficient User-Level Thread Management for Improving Cache Utilization

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 6786))

Abstract

The appearance of the multicore processors and the advancement of multithread programming have lead the new paradigm of the system optimization. Especially, the cache performance has been known as the one of the most important factor of the system optimization. The user-level thread management, the unvirtualized thread and the exception-less system call are introduced to improve the cache utilization of the multithread programming and parallel programming. However, these schemes have some limitations on applications domain. So, we propose the general purpose user-level thread management scheme to reduce the context-switch, CPU-migration and synchronous system call which pollute the amount of caches. We show evaluation of our system on the three workloads. We show the performance improvements of about 10-20% in respect of the CPU, memory and IO intensive workloads and analyze the effects of the three policies and techniques through the experiments.

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References

  1. Fluet, M., Rainey, M., Reppy, J.: A Scheduling Framework for General-Purpose Parallel Languages. In: International Conference on Functional Programming, Victoria, British Columbia, Canada (September 2008)

    Google Scholar 

  2. Liu, R., et al.: Tessellation: Space-time Partitioning in a ManyCore Client OS. In: HotPar, Berkeley, CA (2009)

    Google Scholar 

  3. Fromm, R., Treuhaft, N.: Revisiting the Cache Interference Costs of Context Switching, http://citeseer.ist.psu.edu/252861.html

  4. Zhang, X., Dwarkadas, S., Shen, K.: Towards Practical Page Coloring-based Multicore Cache Management. In: EuroSys, Nuremberg, Germany (2009)

    Google Scholar 

  5. Li, C., Ding, C., Shen, K.: Quantifying the Cost of Context Switch. In: ExpCS, San Diego, CA (2007)

    Google Scholar 

  6. Mogul, J.C., Borg, A.: The Effect of Context Switches on Cache Performance. In: The Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, CA (1991)

    Google Scholar 

  7. Agarwal, A., Hennessy, J.L., Horowitz, M.: Cache Performance of Operating System and Multiprogramming Workloads. ACM Trans. on Computer Systems 6(4), 393–431 (1988)

    Article  Google Scholar 

  8. Tullsen, D., et al.: Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. In: ISCA, Philadelphia, PA (1996)

    Google Scholar 

  9. Anderson, T.E., et al.: Scheduler Activations: Effective Kernel Support for the User-level Management for Parallelism. In: SOSP, Pacific Grove, CA (1991)

    Google Scholar 

  10. Pan, H., Hindman, B., Asanovi, K.: Composing Parallel Software Efficiently with Lithe. In: PLDI, Toronto, Canada (2010)

    Google Scholar 

  11. Soares, L., Stumm, M.: FlexSC: Flexible System Call Scheduling with Exceptionless System Calls. In: OSDI, Vancouver, Canada (2009)

    Google Scholar 

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© 2011 Springer-Verlag Berlin Heidelberg

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Kim, I., Shin, E., Kim, J., Eom, Y.I. (2011). MyUT: Design and Implementation of Efficient User-Level Thread Management for Improving Cache Utilization. In: Murgante, B., Gervasi, O., Iglesias, A., Taniar, D., Apduhan, B.O. (eds) Computational Science and Its Applications - ICCSA 2011. ICCSA 2011. Lecture Notes in Computer Science, vol 6786. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-21934-4_13

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  • DOI: https://doi.org/10.1007/978-3-642-21934-4_13

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-21933-7

  • Online ISBN: 978-3-642-21934-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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