Abstract
NAND flash memories are the most important storage media in mobile computing and tend to be less confined to this area. Nevertheless, it is not mature enough to allow a widespread use. This is due to poor write operations’ performance caused by its internal intricacies. The major constraint of such a technology is the reduced number of erases operations which limits its lifetime. To cope with this issue, state-of-the-art solutions try to level the wear out of the memory to increase its lifetime. These policies, integrated into the Flash Translation Layer (FTL), contribute in decreasing write operation performance. In this paper, we propose to improve the performance and reduce the number of erasures by absorbing them throughout a dual cache system which replaces traditional FTL wear leveling and garbage collection services. C-lash enhances the state-of-the-art FTL performance by more than an order of magnitude for some real and synthetic workloads.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Chung, T., Park, D., Park, S., Lee, D., Lee, S., Song, H.: A Survey of Flash Translation Layer. J. Syst. Archit. 55, 332–343 (2009)
Gupta, A., Kim, Y., Urgaonkar, B.: DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings. In: Proceeding of the 14th international Conference on Architectural Support For Programming Languages and Operating Systems, New York, pp. 229–240 (2009)
Jo, H., Kang, J., Park, S., Kim, J., Lee, J.: FAB: Flash-Aware Buffer Management Policy for Portable Media Players. IEEE Trans. on Consumer Electronics 52, 485–493 (2006)
Kang, S., Park, S., Jung, H., Shim, H., Cha, J.: Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices. IEEE Transactions on Computers 58(6), 744–758 (2009)
Kim, H., Ahn, S.: BPLRU: A Buffer Management Scheme for Improving Random Writes in Flash Storage. In: Baker, M., Riedel, E. (eds.) Proceedings of the 6th USENIX Conference on File and Storage Technologies, CA, pp. 1–14 (2008)
Lee, S., Park, D., Chung, T., Lee, D., Park, S., Song, H.: A Log Buffer-based Flash Translation Layer Using Fully-associative Sector Translation. ACM Trans. Embed. Comput. Syst. 6, 3 (2007)
Park, S., Jung, D., Kang, J., Kim, J., Lee, J.: CFLRU: a Replacement Algorithm for Flash Memory. In: CASES 2006: Proceedings of the 2006 international Conference on Compilers, Architecture and Synthesis For Embedded Systems, Seoul, Korea, pp. 234–241 (2006)
Wu, G., Eckart, B., He, X.: BPAC: An Adaptive Write Buffer Management Scheme for Flash-Based Solid State Drives. In: Proceedings of the IEEE 26th Symposium on Mass Storage Systems and Technologies (2010)
Myers, D.: On the Use of NAND Flash Memory in High-Performance Relational Databases, Master of Sc. Tech. report, Massachussets Institute of technology (2008)
Caulfield, A.M. , Grupp, L. M., Swanson, S.: Gordon: Using Flash Memory to Build Fast, Power-efficient Clusters for Data-intensive Applications. In: ACM Architectural Support for Programming Languages and Operating Systems, Washington, DC (2009)
Stoica, R., Athanassoulis, M., Johnson, R.: Evaluating and Repairing Write Performance on Flash Devices. In: Fifth International Workshop on Data Management on New Hardware (DaMoN 2009), Providence, Rode-Island (2009)
Leventhal, A.: Flash Storage, ACM Queue (2008)
Kim, Y., Tauras, B., Gupta, A., Nistor, D.M., Urgaonkar, B.: FlashSim: A Simulator for NAND Flash-based Solid-State Drives, Tech. Report CSE-09-008, Pensylvania (2009)
Ganger, G.R., Worthington, B.L., Patt, Y.N.: The Disksim Simulation Environment Version 3.0 Reference Manual, Tech. Report CMU-CS-03-102, Pittsburgh (2003)
Forni, G., Ong, C., Rice, C., McKee, K., Bauer, R.J.: Flash Memory Applications. In: Brewer, J.E., Gill, M. (eds.) Nonvolatile Memory Technologies with emphasis on Flash. Series on Microlelectronic Systems. IEEE Press, USA (2007)
Chung, T.S., Park, H.S.: STAFF: A Flash Driver Algorithm Minimizing Block Erasures. Journal of Systems Architectures 53(12), 889–901 (2007)
Park, D., Debnath, B., Du, D.: CFTL: A Convertible Flash Translation Layer with Consideration of Data Access Pattern, Tech Report, University of Minnesota (2009)
M-Systems: Flash Memory Translation Layer for NAND Flash, NFTL (1998)
Wu, C.H., Chang, L.P., Kuo, T.W.: An Efficient B-Tree Layer for Flash-Memory Storage Systems. ACM Trans. On Embedded Computing 6(3) (2007)
Shinohara, T.: Flash Memory Card with Block Memory Address, United States Patent, No. 5,905,993 (1999)
Kim, B.S., Lee, G.Y.: Method of Driving Remapping in Flash Memory and Flash Memory Architecture Suitable Therfor. United States Patent, No. 6,381,176 (2002)
OLTP Traces, UMass Trace Rep, http://traces.cs.umass.edu/index.php/Storage/Storage
Storage Performance Council, http://www.storageperformance.org
Micron: Small Block vs. Large Block NAND Flash Devices, Micron Technical Report TN-29-07 (2007), http://download.micron.com/pdf/technotes/nand/tn2907.pdf
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Boukhobza, J., Olivier, P. (2011). C-Lash: A Cache System for Optimizing NAND Flash Memory Performance and Lifetime. In: Cherifi, H., Zain, J.M., El-Qawasmeh, E. (eds) Digital Information and Communication Technology and Its Applications. DICTAP 2011. Communications in Computer and Information Science, vol 167. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22027-2_50
Download citation
DOI: https://doi.org/10.1007/978-3-642-22027-2_50
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-22026-5
Online ISBN: 978-3-642-22027-2
eBook Packages: Computer ScienceComputer Science (R0)