Abstract
When memory encryption schemes are applied in multiprocessor systems, the systems will confront new problems such as inter-processor communication overhead increasing and cache coherence protocol overhead increasing. A counter cache coherence optimization scheme AOW is proposed to improve cache hit rate. As MESI protocol which makes counter line by four states, AOW marks each counter line using three encryption states, ’Autonomy’, ’Operating’ and ’Waiting’. According to the simulation results, by applying AOW, memory access time decreases, and execution speed of non-AOW method improves obviously.
This work was supported by Franco-Chinese Foundation for Basic and Applied Science (FFCSA).
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References
Lie, D., Mitchell, M., Lincoln, P., Boneh, D., Mitchell, J., Horowitz, M.: Architectural support for copy and tamper resistant software. ACM SIGARCH Computer Architecture 28, 168–177 (2000)
Suh, G., Clarke, D., Gassend, B., van Dijk, M., Devadas, S.: AEGIS: Architecture for tamper-evident and tamper-resistant processing. In: Proceedings of the 17 Int’l Conference on Supercomputing, San Francisco, CA, USA, pp. 160–171 (2003)
Yang, J., Zhang, Y., Gao, L.: Fast secure processor for inhibiting software piracy and tampering. In: The 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-36), San Diego, CA, US (December 2003)
Yan, D.Y.C., Rogers, B., Prvulovic, M.: Improving cost, performance, and security of memory encryption and authentication. In: The 33rd Annual International Symposium on Computer Architecture (ISCA 2006), Boston, MA, US, pp. 179–190 (2006)
Suh, G., Clarke, D., van Dijk, M., Devadas, S.: Caches and hash trees for efficient memory integrity verification. In: Proceedings of the 9th International Symposium on High-Performance Computer Architecture, Anaheim, California, USA, pp. 295–311 (February 2003)
Ravi, S., Raghunathan, A., Kocher, P., Hattangady, S.: Security in embedded systems: Design challenges. ACM Transactions on Embedded Computing Systems (TECS) 3(3), 461–491 (2004)
Skorobogatov, S.P.: Semi-invasive attacks - A new approach to hardware security analysis. Technical Report UCAM-CL-TR-630, University of Cambridge Computer Laboratory (April 2005)
Shi, W., Lee, H.-H.S., Ghosh, M., Lu, C., Boldyreva, A.: High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. In: The Proceedings of the 32nd International Symposium on Computer Architecture, Madison, Wisconsin, pp. 14–24 (June 2005)
Rogers, B., Chhabra, S., Solihin, Y., Prvulovic, M.: Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance- Friendly. In: The Proceedings of the 40th Annual IEEE/ACM Symposium on Microarchitecture, MICRO (December 2007)
Rogers, B., Prvulovic, M., Solihin, Y.: Effective Data Protection for Distributed Shared Memory Multiprocessors. In: The Proceedings of International Conference of Parallel Architecture and Compilation Techniques (PACT), Seattle (September 2006)
Shi, W., Lee, H.-H.S., Ghosh, M., Lu, C.: Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. In: Proceedings of the International Conference on Parallel Architecture and Compilation Techniques, Antibes Juan-les-Pins, France, pp. 123–134 (September 2004)
Zhang, Y., Gao, L., Yang, J., Zhang, X., Gupta, R.: SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. In: The Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA), Washington, DC, USA, pp. 352–362 (2005)
Rogers, B., Prvulovic, M., Solihin, Y.: Efficient data protection for distributed shared memory multiprocessors. In: Proceedings of the 15th international Conference on Parallel Architectures and Compilation Techniques (PACT), Seattle, Washington, USA, pp. 16–20 (September 2006)
Pai, V.S., Ranganathan, P., Adve, S.V.: RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors. In: Proceedings of the Third Workshop on Computer Architecture Education (February 1997)
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Yuanyuan, Z., Junzhong, G. (2011). Using Counter Cache Coherence to Improve Memory Encryptions Performance in Multiprocessor Systems. In: Park, J.J., Lopez, J., Yeo, SS., Shon, T., Taniar, D. (eds) Secure and Trust Computing, Data Management and Applications. STA 2011. Communications in Computer and Information Science, vol 186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22339-6_10
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DOI: https://doi.org/10.1007/978-3-642-22339-6_10
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