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Using Counter Cache Coherence to Improve Memory Encryptions Performance in Multiprocessor Systems

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Part of the book series: Communications in Computer and Information Science ((CCIS,volume 186))

Abstract

When memory encryption schemes are applied in multiprocessor systems, the systems will confront new problems such as inter-processor communication overhead increasing and cache coherence protocol overhead increasing. A counter cache coherence optimization scheme AOW is proposed to improve cache hit rate. As MESI protocol which makes counter line by four states, AOW marks each counter line using three encryption states, ’Autonomy’, ’Operating’ and ’Waiting’. According to the simulation results, by applying AOW, memory access time decreases, and execution speed of non-AOW method improves obviously.

This work was supported by Franco-Chinese Foundation for Basic and Applied Science (FFCSA).

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© 2011 Springer-Verlag Berlin Heidelberg

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Yuanyuan, Z., Junzhong, G. (2011). Using Counter Cache Coherence to Improve Memory Encryptions Performance in Multiprocessor Systems. In: Park, J.J., Lopez, J., Yeo, SS., Shon, T., Taniar, D. (eds) Secure and Trust Computing, Data Management and Applications. STA 2011. Communications in Computer and Information Science, vol 186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-22339-6_10

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  • DOI: https://doi.org/10.1007/978-3-642-22339-6_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-22338-9

  • Online ISBN: 978-3-642-22339-6

  • eBook Packages: Computer ScienceComputer Science (R0)

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