Abstract
Analog integrated circuit design (AICD) is a complex and difficult task, which is usually treated hierarchically. It mainly consists of topological and parametrical level design. Traditional top-down and bottom-up design strategies exhibit several draw-backs for automation. This article proposes an alternative design strategy that separates the high level synthesis (HLS) from circuit level implementation. In the proposed approach, HLS generates, rather than searches for, all valid topologies that can be implemented on a general filter architecture. Circuit level implementation is obtained by automatic architecture-to-circuit mapping. Simulation proves the validity of the proposed automatic design approach.
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Faragó, P., Feştilă, L., Söser, P., Hintea, S. (2011). Automatic Filter Synthesis Based on Tree Generation and Evolutionary Optimization. In: König, A., Dengel, A., Hinkelmann, K., Kise, K., Howlett, R.J., Jain, L.C. (eds) Knowledge-Based and Intelligent Information and Engineering Systems. KES 2011. Lecture Notes in Computer Science(), vol 6884. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-23866-6_48
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DOI: https://doi.org/10.1007/978-3-642-23866-6_48
Publisher Name: Springer, Berlin, Heidelberg
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