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A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors

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Computer Safety, Reliability, and Security (SAFECOMP 2011)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 6894))

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Abstract

This paper presents a dynamically scheduled pipeline structure for chip multiprocessors (CMPs). This technique exploits existing Simultaneous Multithreading (SMT), superscalar chip multiprocessors’ redundancy to provide low-overhead, and broad coverage of faults at the cost of performance degradation for processors. This pipeline structure operates in two modes: 1) high-performance and 2) highly-reliable. In high-performance mode, each core works as a real SMT, superscalar processor. Whereas, the main contribution of the highly-reliable mode is: 1) To enhance the reliability of the system without adding extra redundancy strictly for fault tolerance, 2) To detect both transient and permanent faults, and 3) To recover existing faults. The experimental results show that the diagnosis mechanism quickly and accurately diagnoses faults. The fault detection latency for this technique is equal to the pipeline length of the processor, while it provides high fault detection coverage. Moreover, the reliable processor can function quite capably in the presence of both transient and permanent faults, despite of not using redundancy beyond which is already available in a modern microprocessor. Also, in the highly-reliable mode, the static and dynamic power consumption is declined by 25% and 36%, respectively.

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Authors and Affiliations

  1. Department of Computer Engineering and Information Technology, Amirkabir University of Technology (Tehran Polytechnic), Ireland

    Hananeh Aliee & Hamid Reza Zarandi

Authors
  1. Hananeh Aliee
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  2. Hamid Reza Zarandi
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Editors and Affiliations

  1. Ansaldo STS, Via Argine, 425, 80147, Napoli, Italy

    Francesco Flammini

  2. Italian Association Critical Infrastructure (AIIC), Rome, Italy

    Sandro Bologna

  3. Dipartimento di Informatica e Sistemistica, UniversitĂ  di Napoli Federico II, Via Claudio, 21, Napoli, Italy

    Valeria Vittorini

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Aliee, H., Zarandi, H.R. (2011). A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors. In: Flammini, F., Bologna, S., Vittorini, V. (eds) Computer Safety, Reliability, and Security. SAFECOMP 2011. Lecture Notes in Computer Science, vol 6894. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24270-0_24

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  • DOI: https://doi.org/10.1007/978-3-642-24270-0_24

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-24269-4

  • Online ISBN: 978-3-642-24270-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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