Skip to main content

Design of Dual-Shared DRAM Controller Based on Switch

  • Conference paper
  • 895 Accesses

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 238))

Abstract

According to the harsh desire to share memory of multi-processors system on chip, this paper presents a switch-based Dual-Shared DRAM Controller (DSMC). The DSMC is composed of center control module, two IP(interface to processor) module, two ID(interface to DRAM) module, CM(Clock Manager) module, and IR(initialize and refresh) module. It use two memories as shared memory and resolves conflicts which may occur when two processors access the same memory, and actualizes every control to DRAM, such as initializing, refreshing, reading and writing. At last, it makes two processors access the shared memories coinstantaneous at will.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Zhao, Q., Li, W.: Analyzing multiprocessor structure. Microcomputer Applications 26(1), 113–115 (2005)

    Google Scholar 

  2. Lee, K.-B., Lin, T.-C., Jen, C.-W.: An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. IEEE Transactions on Circuits and Systems for Video Technology 15(5), 620–633 (2005)

    Article  Google Scholar 

  3. Acacio, M.E., Gonza lez, J.: An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Transactions on Parallel and Distributed Systems 15(8), 755–768 (2004)

    Article  Google Scholar 

  4. Li, w.: Control System Based on Switching of Shared Dynamic Memory with dual-processor. [Master thesis], Taiyuan University of Technology (2007)

    Google Scholar 

  5. Zhang, N., Zhang, P.-y., Liu, X.-c., Jiang, X.-y.: FPGA-based DDR SDRAM Controller Implemention. Computer Engineering and Application (24), 87–90 (2006)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Li, Y., Zhang, B., Han, X., Zhang, G. (2011). Design of Dual-Shared DRAM Controller Based on Switch. In: Zhiguo, G., Luo, X., Chen, J., Wang, F.L., Lei, J. (eds) Emerging Research in Web Information Systems and Mining. WISM 2011. Communications in Computer and Information Science, vol 238. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24273-1_41

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-24273-1_41

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-24272-4

  • Online ISBN: 978-3-642-24273-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics