Skip to main content
SpringerLink
Log in

A Minimal Average Accessing Time Scheduler for Multicore Processors

  • Conference paper
Algorithms and Architectures for Parallel Processing (ICA3PP 2011)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7017))

Abstract

In this paper, we study and analyze process scheduling for multicore processors. It is expected that hundreds of cores will be integrated on a single chip, known as a Chip Multiprocessor (CMP). However, operating system process scheduling, one of the most important design issue for CMP systems, has not been well addressed. We define a model for future CMPs, based on which a minimal average accessing time scheduling algorithm is proposed to reduce on-chip communication latencies and improve performance. The impact of memory access and inter process communication (IPC) in scheduling are analyzed. We explore six typical core allocation strategies. Results show that, a strategy with the minimal average accessing time of both core-core and core-memory outperforms other strategies, the overall performance for three applications (FFT, LU and H.264) has improved for 8.23%, 4.81% and 10.21% respectively comparing with other strategies.

This work is supported by Academy of Finland and Nokia Foundation.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Benini, L., Micheli, G.D.: Networks on chips: A new soc paradigm. IEEE Computer 35(1), 70–78 (2002)

    Article  Google Scholar 

  2. Intel: Single-chip cloud computer (May 2010), http://techresearch.intel.com/articles/Tera-Scale/1826.htm

  3. Corporation, T. (August 2010), http://www.tilera.com

  4. Scott, T.L., Mary, K.V.: The performance of multiprogrammed multiprocessor scheduling algorithms. In: Proc. of the 1990 ACM SIGMETRICS, pp. 226–236 (1990)

    Google Scholar 

  5. Hakem, M., Butelle, F.: Dynamic critical path scheduling parallel programs onto multiprocessors. In: Proceedings of 19th IEEE IPDPS, p. 203b (2005)

    Google Scholar 

  6. Sharma, D.D., Pradhan, D.K.: Processor allocation in hypercube multicomputers: Fast and efficient strategies for cubic and noncubic allocation. IEEE TPDS 6(10), 1108–1123 (1995)

    Google Scholar 

  7. Laudon, J., Lenoski, D.: The sgi origin: a ccnuma highly scalable server. In: Proc. of the 24th ISCA, pp. 241–251 (June 1997)

    Google Scholar 

  8. Abts, D., Jerger, N.D.E., Kim, J., Gibson, D., Lipasti, M.H.: Achieving predictable performance through better memory controller placement in many-core cmps. In: Proc. of the 36th ISCA (2009)

    Google Scholar 

  9. Chen, Y.J., Yang, C.L., Chang, Y.S.: An architectural co-synthesis algorithm for energy-aware network-on-chip design. J. Syst. Archit. 55(5-6), 299–309 (2009)

    Article  Google Scholar 

  10. Hu, J., Marculescu, R.: Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In: DATE 2004 (2004)

    Google Scholar 

  11. Lei, T., Kumar, S.: A two-step genetic algorithm for mapping task graphs to a network on chip architecture. In: DSD, pp. 180–187 (September 2003)

    Google Scholar 

  12. Global, H.: Ddr 2 memory controller ip core for fpga and asic (June 2010), http://www.hitechglobal.com/ipcores/ddr2controller.htm

  13. Kim, Y., Han, D., Mutlu, O., Harchol-Balter, M.: Atlas: A scalable and high-performance scheduling algorithm for multiple memory controllers. In: 2010 IEEE 16th HPCA, pp. 1–12 (2010)

    Google Scholar 

  14. Awasthi, M., Nellans, D.W., Sudan, K., Balasubramonian, R., Davis, A.: Handling the problems and opportunities posed by multiple on-chip memory controllers. In: Proceedings of the 19th PACT, pp. 319–330. ACM, New York (2010)

    Google Scholar 

  15. Gaeke, B.R., Husbands, P., Li, X.S., Oliker, L., Yelick, K.A., Biswas, R.: Memory-intensive benchmarks: Iram vs. cache-based machines. In: Proc. of the 16th IPDPS

    Google Scholar 

  16. Schmid, P., Roos, A.: Core i7 memory scaling: From ddr3-800 to ddr3-1600 (2009), Tom’s Hardware

    Google Scholar 

  17. Bailey, D.H.: Ffts in external or hierarchical memory. The Journal of Supercomputing 4, 23–35 (1990), doi:10.1007/BF00162341

    Article  Google Scholar 

  18. Woo, S.C., Singh, J.P., Hennessy, J.L.: The performance advantages of integrating block data transfer in cache-coherent multiprocessors. In: ASPLOS-VI, pp. 219–229. ACM, New York (1994)

    Chapter  Google Scholar 

  19. Bienia, C., Kumar, S., Singh, J.P., Li, K.: The parsec benchmark suite: characterization and architectural implications. In: Proc. of 17th PACT (October 2008)

    Google Scholar 

  20. Xu, T., Yin, A., Liljeberg, P., Tenhunen, H.: A study of 3d network-on-chip design for data parallel h.264 coding. In: NORCHIP, pp. 1–6 (November 2009)

    Google Scholar 

  21. Pereira, F.C., Ebrahimi, T.: The MPEG-4 Book. Prentice Hall, Englewood Cliffs (2002)

    Google Scholar 

  22. Magnusson, P., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., Werner, B.: Simics: A full system simulation platform. Computer 35(2), 50–58 (2002)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Turku Center for Computer Science, Joukahaisenkatu 3-5 B, 20520, Turku, Finland

    Thomas Canhao Xu, Pasi Liljeberg & Hannu Tenhunen

  2. Department of Information Technology, University of Turku, 20014, Turku, Finland

    Thomas Canhao Xu, Pasi Liljeberg & Hannu Tenhunen

Authors
  1. Thomas Canhao Xu
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Pasi Liljeberg
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Hannu Tenhunen
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. School of Information Technology, Deakin University, Melbourne Burwood Campus, 221 Burwood Highway, 3125, Burwood, VIC, Australia

    Yang Xiang  & Wanlei Zhou  & 

  2. ICAR-CNR and University of Calabria, Via P. Bucci 41 C, 87036, Rende, CS, Italy

    Alfredo Cuzzocrea

  3. School of Information Technology, Deakin University, Geelong Waurn Ponds Campus, Pigdons Road, 3217, Geelong, VIC, Australia

    Michael Hobbs

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Xu, T.C., Liljeberg, P., Tenhunen, H. (2011). A Minimal Average Accessing Time Scheduler for Multicore Processors. In: Xiang, Y., Cuzzocrea, A., Hobbs, M., Zhou, W. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2011. Lecture Notes in Computer Science, vol 7017. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24669-2_28

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-24669-2_28

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-24668-5

  • Online ISBN: 978-3-642-24669-2

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation