Abstract
Programs co-running on cores share resources on multi-core processor systems. It is now well known that interference between the programs arising from the sharing may result in severe performance degradations. It is the objective of recent research in system scheduling to be aware of shared resource requirements of the running programs (threads). To this end AKULA is a toolset recently developed that provides a platform for experiments and developing thread scheduling algorithms on multi-core processors. In AKULA a bootstrapping module works on the basis of previously collected performance data of programs to simulate program execution on multi-cores. In this paper we describe a different approach where that augments such a bootstrapping module with a model built using machine learning techniques. The proposed model will extend the bootstrapping module’s ability to predict degradation in performance due to sharing where previous performance data is not available for pairing /co-scheduling of applications. Also the proposed approach allows greater scalability for variable number of processor cores sharing the resources.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Zhuravlev, S., Blagodurov, S., Fedorova, A.: Addressing Shared Resource Contention in Multicore Processors via Scheduling. In: Fifteenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2010), Pittsburgh, Pennsylvania, USA, pp. 129–142 (March 2010)
Rai, J.K., Negi, A., Wankar, R., Nayak, K.D.: A Machine Learning based Meta-Scheduler for Multi-core Processors. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 1(4), 46–59 (2010)
Zhuravlev, S., Blagodurov, S., Fedorova, A.: AKULA: A Toolset for Experimenting and Developing Thread Placement Algorithms on Multicore Systems. In: Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT 2010), Vienna, Austria, pp. 249–260 (2010)
Intel® 64 and IA-32 Architectures Software Developer’s Manuals, http://www.intel.com/products/processor/manuals
AMD-phenom-processor-model-numbers-feature-comparison, http://www.amd.com/us/products/desktop/processors/phenom/Pages/AMD-phenom-processor-model-numbers-feature-comparison.aspx
Rai, J.K., Negi, A., Wankar, R., Nayak, K.D.: Performance Prediction on Multi-core Processors. In: The IEEE 2010 International Conference on Computational Intelligence, Communication Systems and Networks (CICN 2010), Bhopal, India, November 26-28, pp. 633–637 (2010)
Eranian, S.: Perfmon2: The Hardware-based Performance Monitoring Interface for Linux. In: 2006 Linux Symposium, vol. 1, pp. 269–288 (2006)
Standard performance evaluation corporation. SPEC CPU2006, http://www.spec.org/cpu2006/
Witten, I.H., Frank, E.: Data Mining: Practical machine learning tools and techniques, 2nd edn. Morgan Kaufmann, San Francisco (2005)
Sherwood, T., Perelman, E., Hamerly, G., Sair, S., Calder, B.: Discovering and Exploiting Program Phases. IEEE Micro 23(6), 84–93 (2003)
Poonacha, K., Kathirgamar, A., Kunle, O.: Niagara, a 32-way Multithreaded Sparc Processor. IEEE Micro, 21–29 (March-April 2005)
Niagara2: A Highly Threaded Server-on-a-Chip, http://www.opensparc.net/pubs/preszo/06/04-Sun-Golla.pdf
BIOS and Kernel Developer’s Guide (BKDG) For AMD Family 10h Processors, http://developer.amd.com/documentation/guides/pages/default.aspx
Eranian, S.: (on mailing list) Re: [perfmon2] CORE_0_SELECT Umask for L3 events on AMD F10h (2011), http://permalink.gmane.org/gmane.comp.linux.perfmon2.devel/3014
Revision Guide for AMD Family 10h Processors 41322 Rev. 3.82 (2011), support.amd.com/us/Processor_TechDocs/41322.pdf
Chandra, D., Guo, F., Kim, S., Solihin, Y.: Predicting Inter-Thread Cache Contenton on a Chip Multi-Processor Architecture. In: Proceedings of the 11th International Symposium on High Performance Computer Architecture, HPCA 2005, San Francisco, CA, USA, pp. 340–351 (2005)
Zhuravlev, S., Blagodurov, S., Fedorova, A.: Addressing Shared Resource Contention in Multicore Processors via Scheduling. In: Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, pp. 129–142 (2010)
Luk, C.K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V.J., Hazelwood, K.: Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. In: Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2005, pp. 190–200 (2005)
Hoste, K., Eeckhout, L.: Microarchitecture-Independent Workload Characterization. IEEE Micro 27(3), 63–72 (2007)
Xu, C., Chen, X., Dick, R.P., Mao, Z.M.: Cache Contention and Application Performance Prediction for Multi-Core Systems. In: Proceedings of the 2010 IEEE International Symposium on Performance Analysis of Systems and Softwares IEEE ISPASS 2010, White Plains NY, USA, pp. 76–86 (2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rai, J.K., Negi, A., Wankar, R. (2011). Machine Learning Based Performance Prediction for Multi-core Simulation. In: Sombattheera, C., Agarwal, A., Udgata, S.K., Lavangnananda, K. (eds) Multi-disciplinary Trends in Artificial Intelligence. MIWAI 2011. Lecture Notes in Computer Science(), vol 7080. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25725-4_21
Download citation
DOI: https://doi.org/10.1007/978-3-642-25725-4_21
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-25724-7
Online ISBN: 978-3-642-25725-4
eBook Packages: Computer ScienceComputer Science (R0)