Novel Low-Voltage Small-Area I/O Buffer for Mixed-Voltage Application

Abstract

Novel mixed-voltage I/O buffer with fast low-voltage operation and small-area realization is proposed. The I/O buffer provides reduced latency at low supply voltages by eliminating the voltage swing degradation at timing-critical nets. The buffer also provides smaller layout area by avoiding dedicated bulky circuits like dynamic gate-bias circuit (DGBC) and hot-carrier prevention circuit (HCPC). Evaluation results in 130-nm CMOS process indicated that the proposed mixed-voltage I/O buffer achieves up to 52% reduction on latency and up to 39% reduction on layout area as compared to conventional mixed-voltage I/O buffers.