Abstract
This paper presents the complexity analysis of digit serial finite field multipliers over GF(2m) on FPGAs. Instead of discussing the complexity by using AND and XOR gates as primitives, we present the complexity analysis directly based on FPGA primitives, e.g., Look-Up-Tables (LUTs). Given digit size d, the number of LUTs and the level of LUT delay are estimated. The previous ASIC based complexity analysis shows the optimum digit size (for Area-Time-Product) is 2l − 1. We show in this work that the optimum digit sizes are different on FPGAs. They are those digits ds which satisfy \(\lceil \frac{m}{d-1} \rceil \neq \lceil \frac{m}{d} \rceil\). We also validate our analysis with experimental results on GF(2163) and GF(2233).
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Zhou, G., Li, L., Michalik, H. (2012). Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2012. Lecture Notes in Computer Science, vol 7199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28365-9_11
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DOI: https://doi.org/10.1007/978-3-642-28365-9_11
Publisher Name: Springer, Berlin, Heidelberg
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