Abstract
One of the main challenges in the design of hardware accelerators is the efficient access of data from the external memory. Improving and optimizing the functionality of the memory controller between the external memory and the accelerators is therefore critical. In this paper, we advance toward this goal by proposing PPMC, the Programmable Pattern-based Memory Controller. This controller supports scatter-gather and strided 1D, 2D and 3D accesses with programmable tiling. Compared to existing solutions, the proposed system provides better performance, simplifies programming access patterns and eases software integration by interfacing to high-level programming languages. In addition, the controller offers an interface for automating domain decomposition via tiling. We implemented and tested PPMC on a Xilinx ML505 evaluation board using a MicroBlaze soft-core as the host processor. The evaluation uses six memory intensive application kernels: Laplacian solver, FIR, FFT, Thresholding, Matrix Multiplication, and 3D-Stencil. The results show that the PPMC-enhanced system achieves at least 10x speed-ups for 1D, 2D and 3D memory accesses as compared to a non-PPMC based setup.
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References
Roth, A., Sohi, G.S.: Effective jump-pointer prefetching for linked data structures. In: ISCA 1999 Proceedings of the 26th Annual International Symposium on Computer Architecture (May 1999)
Chai, S.M., Bellas, N., Dwyer, M., Linzmeier, D.: Stream Memory Subsystem in Reconfigurable Platforms (2006)
Altera Corporation: Scatter-Gather DMA Controller Core, Quartus II 9.1 (November 2009)
Gannon, D., Jalby, W., Gallivan, K.: Strategies for Cache and Local Memory Management by Global Program Rransformation. Journal of Parallel and Distributed Computing
Gou, C., Kuzmanov, G., Gaydadjiev, G.N.: SAMS multi-layout memory: providing multiple views of data to boost SIMD performance (2010)
Coole, J., Wernsing, J., Stitt, G.: A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. In: International Conference on Reconfigurable Computing and FPGAs (2009)
Carter, J., Hsieh, W., Stoller, L., Swanson, M., Zhang, L., Brunvand, E., Davis, A., Kuo, C.-C., Kuramkote, R., Parker, M., Schaelicke, L., Tateyama, T.: Impulse: Building a Smarter Memory Controller. In: Fifth International Symposium on High Performance Computer Architecture, HPCA-5 (January 1999)
Farkas, K.I., Jouppi, N.P., Chow, P.: How Useful Are Non-blocking Loads, Stream Buffers, and Speculative Execution in Multiple Issue Processors? (1995)
Lattice Semiconductor Corporation: Scatter-Gather Direct Memory Access Controller IP Core Users Guide (October 2010)
Shafiq, M., Pericas, M., de la Cruz, R., Araya-Polo, M., Navarro, N., Ayguade, E.: Exploiting Memory Customization in FPGA for 3D Stencil Computations (2009)
Jouppi, N.: Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers (1990)
Riverside Optimizing Compiler for Configurable Computing (ROCCC), http://www.jacquardcomputing.com/roccc/
Derrien, S., Rajopadhye, S.: Loop Tiling for Reconfigurable Accelerators. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, pp. 398–408. Springer, Heidelberg (2001)
Stitt, G., Chaudhari, G., Coole, J.: Traversal Caches: A First Step Towards FPGA Acceleration of Pointer-Based Data Structures (2008)
Xilinx: Channelized Direct Memory Access and Scatter Gather (February 2010)
Xilinx: Memory Interface Solutions (December 2009)
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Hussain, T., Shafiq, M., Pericàs, M., Navarro, N., Ayguadé, E. (2012). PPMC: A Programmable Pattern Based Memory Controller. In: Choy, O.C.S., Cheung, R.C.C., Athanas, P., Sano, K. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2012. Lecture Notes in Computer Science, vol 7199. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28365-9_8
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DOI: https://doi.org/10.1007/978-3-642-28365-9_8
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