Skip to main content

A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors

  • Chapter

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 6805))

Abstract

3-D integration presents many new opportunities for architects and embedded systems designers. However, 3-D integration has not yet been explored by the cryptographic hardware community. Traditionally, crypto co-processors have been implemented as a separate die or by utilizing one or more cores in a chip multiprocessor. These methods have their drawbacks and limitations in terms of tamper-resistance, side-channel immunity and performance. In this work we propose a new class of co-processors that are “snapped-on” to the main processor using 3-D integration, and we investigate their security ramifications. These 3-D co-processors hold many advantages over previous implementations. This paper begins with an overview of 3-D integration and its prior applications. We then outline security threat models relevant to crypto co-processors and discuss the advantages and disadvantages of using a dedicated 3-D crypto co-processor compared to traditional, commodity, off-chip crypto co-processors. We also discuss the performance improvements that can be gained from using a 3-D approach.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Ababei, C., Feng, Y., Goplen, B., Mogal, H., Zhang, T., Bazargan, K., Sapatnekar, S.: Placement and Routing in 3D Integrated Circuits. IEEE Design and Test of Computers 22(6), 520–531 (2005)

    Article  Google Scholar 

  2. Acıiçmez, O., Seifert, J.P., Koc, C.K.: Micro-architectural cryptanalysis. IEEE Security and Privacy Magazine 5(4) (July-August 2007)

    Google Scholar 

  3. Aciicmez, O., Schindler, W., Koç, Ç.K.: Improving Brumley and Boneh timing attack on unprotected SSL implementations. In: Proceedings of the 12th ACM Conference on Computer and Communications Security, pp. 139–146 (November 2005)

    Google Scholar 

  4. Aciicmez, O., Seifert, J.P., Koç, Ç.K.: Micro-architectural cryptanalysis. IEEE Security & Privacy 5(4), 62–64 (2007)

    Article  Google Scholar 

  5. Agrawal, D., Archambeault, B., Rao, J.R., Rohatgi, P.: The EM side-channel(s). In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 29–45. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  6. Akturk, A., Goldsman, N., Metze, G.: Self-Consistent Modeling of Heating and MOSFET Performance in 3-D Integrated Circuits. IEEE Transactions on Electron Devices 52(11), 2395–2403 (2005)

    Article  Google Scholar 

  7. Banerjee, K., Souri, S.J., Kapur, P., Saraswat, K.C.: 3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration. Proceedings of the IEEE 89(5), 602–633 (2001)

    Article  Google Scholar 

  8. Benkart, et al.: 3D Chip Stack Technology Using Through-Chip Interconnects. IEEE Design and Test of Compus 22(6), 512–518 (2005)

    Article  Google Scholar 

  9. Bernstein, D.J.: Cache-timing attacks on AES (April 2005), Revised version of earlier 2004-11 version, http://cr.yp.to/antiforgery/cachetiming-20050414.pdf

  10. Black, B., Annavaram, M., Brekelbaum, N., DeVale, J., Jiang, L., Loh, G.H., McCauley, D., Morrow, P., Nelson, D.W., Pantuso, D., Reed, P., Rupley, J., Shankar, S., Shen, J., Webb, C.: Die Stacking (3D) Microarchitecture. In: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 469–479 (December 2006)

    Google Scholar 

  11. Boneh, D., DeMillo, R.A., Lipton, R.J.: On the importance of checking cryptographic protocols for faults. In: Fumy, W. (ed.) EUROCRYPT 1997. LNCS, vol. 1233, pp. 37–51. Springer, Heidelberg (1997)

    Google Scholar 

  12. Brumley, D., Boneh, D.: Remote Timing Attacks Are Practical. In: Proceedings of the 12th USENIX Security Symposium (2003)

    Google Scholar 

  13. Davis, W.R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A.M., Steer, M., Franzon, P.D.: Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Design and Test of Computers 22(6), 498–510 (2005)

    Article  Google Scholar 

  14. Gandolfi, K., Mourtel, C., Olivier, F.: Electromagnetic analysis: Concrete results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  15. Groger, M., Harb, S.M., Morris, D., Eisenstadt, W.R., Puligundla, S.: High Speed I/O and Thermal Effect Characterization of 3D Stacked ICs. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), pp. 1–5 (September 2009)

    Google Scholar 

  16. Gueron, S.: White paper: Advanced encryption standard (AES) instructions set, Intel corporation (July 2008)

    Google Scholar 

  17. Alex Halderman, J., Schoen, S.D., Heninger, N., Clarkson, W., Paul, W., Calandrino, J.A., Feldman, A.J., Appelbaum, J., Felten, E.W.: Lest we remember: Cold-boot attacks on encryption keys. In: Proceedings of the USENIX Security Symposium, Sec 2008 (June 2008)

    Google Scholar 

  18. Hollosi, B., Zhang, T., Nair, R.S.P., Xie, Y., Di, J., Smith, S.: Investigation and Comparison of Thermal Distribution in Synchronous and Asynchronous 3D ICs. In: Proceedings of the IEEE International Conference on 3D System Integration (3D IC), pp. 1–5 (September 2009)

    Google Scholar 

  19. Jacob, P., Erdogan, O., Zia, A., Belemjian, P.M., Kraft, R.P., McDonald, J.F.: Predicting the performance of a 3D processor-memory chip stack. IEEE Design and Test of Computers 22(6), 540–547 (2005)

    Article  Google Scholar 

  20. Kleiner, M.B., Kühn, S.A., Weber, W.: Performance Improvement of the Memory Hierarchy of RISC Systems by Applications of 3-D Technology. In: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2305–2308 (1995)

    Google Scholar 

  21. Kocher, P.C., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)

    Google Scholar 

  22. Kocher, P.C.: Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104–113. Springer, Heidelberg (1996)

    Google Scholar 

  23. Kumagai, J.: Chip detectives. IEEE Spectrum 37(11), 43 (2000)

    Article  MathSciNet  Google Scholar 

  24. Liu, C.C., Ganusov, I., Burtscher, M., Tiwari, S.: Bridging the Processor-Memory Performance Gap with 3D IC Technology. IEEE Design and Test 22(6), 556–564 (2005)

    Article  Google Scholar 

  25. Loh, G.D.: 3D-Stacked Memory Architectures for Multi-Core Processors. In: Proceedings of the 35th Annual International Symposium on Computer Architecture (ISCA), pp. 453–464 ( June 2008)

    Google Scholar 

  26. Loi, G.L., Agrawal, B., Srivastava, N., Lin, S.-C., Sherwood, T., Banerjee, K.: A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy. In: Proceedings of the 43nd Design Automation Conference, DAC (June 2006)

    Google Scholar 

  27. Massit, C., Gerard, N.: Three-dimensional multichip module. United State Patent, US 5373189 (December 1994)

    Google Scholar 

  28. Matsumoto, K., Taira, Y.: Thermal resistance measurements of interconnections and modeling of thermal conduction path, for the investigation of the thermal resistance of a three- dimensional (3D) chip stack. In: Proceedings of the 13th IEEE International Symposium on Consumer Electronics (ISCE 2009), pp. 598–602 ( July 2009)

    Google Scholar 

  29. Miura, et al.: A 195Gb/s 1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power Control Scheme. In: IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 264–265 (February 2005)

    Google Scholar 

  30. Mysore, S., Agrawal, B., Lin, S.C., Srivastava, N., Banerjee, K., Sherwood, T.: Introspective 3-D chips. In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA (October 2006)

    Google Scholar 

  31. National Security Agency (NSA). NSA Suite B Cryptography, http://www.nsa.gov/ia/programs/suiteb_cryptography

  32. National Institute of Standards and Technology (NIST). Suite B Implementer’s Guide to NIST SP 800-56A. CryptoBytes, RSA Laboratories 4(1), 6–10 (2009)

    Google Scholar 

  33. Percival, C.: Cache missing for fun and profit. In: Proceedings of the Technical BSD Conference (BSDCan 2005), Ottowa, Canada (May 2005)

    Google Scholar 

  34. Puttaswamy, K., Loh, G.H.: Implementing Caches in a 3D Technology for High Performance Processors. In: IEEE International Conference on Computer Design (ICCD 2006), pp. 525–532 (2005)

    Google Scholar 

  35. Puttaswamy, K., Loh, G.H.: Thermal analysis of a 3D die-stacked high-performance microprocessor. In: Proceedings of the 16th ACM Great Lakes symposium on VLSI, pp. 19–24 (May 2006)

    Google Scholar 

  36. Quisquater, J.-J., Samyde, D.: ElectroMagnetic analysis (EMA): Measures and counter-measures for smart cards. In: Attali, S., Jensen, T. (eds.) E-smart 2001. LNCS, vol. 2140, pp. 200–210. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  37. Quisquater, J.-J., Samyde, D.: Side Channel Cryptanalysis. In: Proceedings of the Workshop on the Security of Communications on the Internet (SECI), pp. 179–184 (September 2002)

    Google Scholar 

  38. Saha, D., Mukhopadhyay, D., RoyChowdhury, D.: Cryptographic processors - a survey. Proceedings of the IEEE 94(2), 357–369 (2006)

    Article  Google Scholar 

  39. Saha, D., Mukhopadhyay, D., RoyChowdhury, D.: A Diagonal Fault Attack on the Advanced Encryption Standard. Cryptology ePrint Archive 581 (2009)

    Google Scholar 

  40. Soden, J.M., Anderson, R.E.: IC failure analysis: Techniques and tools for quality and reliability improvement. Microelectronics and Reliability 35(3), 429–453 (1995)

    Article  Google Scholar 

  41. Sun, H., Liu, J., Anigundi, R.S., Zheng, N., Lu, J.-Q., Rose, K., Zhang, T.: 3D DRAM design and application to 3D multicore systems. IEEE Design and Test of Computers 26(5) (September 2009)

    Google Scholar 

  42. Tam, P.: Ottawa firm rescues data from Swissair black box. The Ottawa Citizen (March 21, 2000)

    Google Scholar 

  43. Tsai, Y.-F., Xie, Y., Vijaykrishnan, N., Irwin, M.J.: Three-Dimensional Cache Design Exploration Using 3DCacti. In: IEEE International Conference on Computer Design. IEEE, Los Alamitos (2005)

    Google Scholar 

  44. Wheeler, B., Byrne, J.: A Guide to Processors for Network Security. Technical Report, The Linley Group (August 2010)

    Google Scholar 

  45. Wu, L., Weaver, C., Austin, T.: CryptoManiac: A Fast Flexible Architecture for Secure Communication. In: Proceedings of the 28th Annual International Symposium on Computer Architecture (ISCA), pp. 110–119 (June-July 2001)

    Google Scholar 

  46. Yoshikawa, H., Kawasaki, A., Iizuka, T., Nishimura, Y., Tanida, K., Akiyama, K., Sekiguchi, M., Matsuo, M., Fukuchi, S., Takahashi, K.: Chip scale camera module (CSCM) using through-silicon-via (TSV). In: Proceedings of the International Solid-State Circuits Conference (ISSCC), San Francisco, CA (February 2009)

    Google Scholar 

  47. Zeng, A., Lu, J., Rose, K., Gutmann, R.J.: First-Order Performance Prediction of Cache Memory with Wafer-Level 3D Integration. IEEE Design and Test of Computers 22(6), 548–555 (2005)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Valamehr, J. et al. (2012). A Qualitative Security Analysis of a New Class of 3-D Integrated Crypto Co-processors. In: Naccache, D. (eds) Cryptography and Security: From Theory to Applications. Lecture Notes in Computer Science, vol 6805. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-28368-0_24

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-28368-0_24

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-28367-3

  • Online ISBN: 978-3-642-28368-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics