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Monitoring Data Structures Using Hardware Transactional Memory

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Runtime Verification (RV 2011)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 7186))

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Abstract

The robustness of software systems is adversely affected by programming errors and security exploits that corrupt heap data structures. In this paper, we present the design and implementation of TxMon, a system to detect such data structure corruptions. TxMon leverages the concurrency control machinery implemented by hardware transactional memory (HTM) systems to additionally enforce programmer-specified consistency properties on data structures at runtime. We implemented a prototype version of TxMon using an HTM system (LogTMSE) and studied the feasibility of applying TxMon to enforce data structure consistency properties on several benchmarks. Our experiments show that TxMon is effective at monitoring data structure properties, imposing tolerable runtime performance overheads.

Funded in part by NSF CNS grants 0728937, 0831268, 0915394 and 0952128. Most of this work was done when A. Baliga was affiliated with Rutgers University.

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References

  1. Issues – memcached – project hosting on Google code, http://code.google.com/p/memcached/issues

  2. Memcached: A distributed memory object caching system, http://memcached.org

  3. Stanford transactional coherence and consistency project, http://tcc.stanford.edu

  4. ClamAV multiple vulnerabilities, Secunia Advisories – SA28117 (December 2007)

    Google Scholar 

  5. Adi-Tabatabai, A., Lewis, B.T., Menon, V., Murphy, B.R., Saha, B.: Compiler and runtime support for efficient software transactional memory. In: ACM Conf. on Prog. Lang. Design & Impl. (June 2006)

    Google Scholar 

  6. Aho, A.V., Corasick, M.J.: Efficient string matching: An aid to bibliographic search. Comm. ACM (1975)

    Google Scholar 

  7. Bobba, J., Xiong, W., Yen, L., Hill, M.D., Wood, D.A.: StealthTest: Low overhead online software testing using transactional memory. In: Intl. Symp. Parallel Architectures and Compilation Techniques (September 2009)

    Google Scholar 

  8. Cascaval, C., Blundell, C., Michael, M., Cain, H.W., Wu, P., Chiras, S., Chatterjee, S.: Software transactional memory: Why is it only a research toy? Comm. ACM (2008)

    Google Scholar 

  9. Ceze, L., Tuck, J., Cascaval, C., Torrellas, J.: Bulk disambiguation of speculative threads in multiprocessors. In: Intl. Symp. Comp. Arch. (June 2006)

    Google Scholar 

  10. Chaudhry, S.: Rock: A third generation 65nm, 16-core, 32 thread + 32 scout-threads CMT SPARC processor. In: HotChips (2008)

    Google Scholar 

  11. Chung, J., Baek, W., Bronson, N.G., Seo, J., Kozyrakis, C., Olukotun, K.: ASeD: Availability, security, and debugging using transactional memory (poster). In: SPAA (June 2008)

    Google Scholar 

  12. Chung, J., Dalton, M., Kannan, H., Kozyrakis, C.: Thread-safe dynamic binary translation using transactional memory. In: IEEE Symp. High Perf. Comp. Arch. (February 2008)

    Google Scholar 

  13. Ernst, M.D., Perkins, J.H., Guo, P.J., McCamant, S., Pacheco, C., Tschantz, M.S., Xiao, C.: The Daikon system for dynamic detection of likely invariants. Sci. Comp. Prog. (December 2007)

    Google Scholar 

  14. Goetz, B.: Optimistic thread concurrency: Breaking the scale barrier, Azul Systems Technical Whitepaper (2009)

    Google Scholar 

  15. Hammer, M., McLeod, D.: A framework for data base semantic integrity. In: Intl. Conf. Soft. Engg. (1976)

    Google Scholar 

  16. Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistency. In: Intl. Symp. Comp. Arch. (June 2004)

    Google Scholar 

  17. Harris, T., Peyton-Jones, S.: Transactional memory with data invariants. In: TRANSACT (June 2006)

    Google Scholar 

  18. Herlihy, M., Moss, J.E.B.: Transactional support for lock free data structures. In: Intl. Symp. Comp. Arch. (1993)

    Google Scholar 

  19. Hill, M.D., Hower, D., Moore, K.E., Swift, M.M., Volos, H., Wood, D.A.: A case for deconstructing hardware transactional memory systems. In: UW-Madison Computer Sciences Technical Report CS-TR-2007-1594 (2007)

    Google Scholar 

  20. Larus, J.R., Rajwar, R.: Transactional Memory. Synthesis Lectures on Comp. Arch. Morgan Claypool (2006)

    Google Scholar 

  21. Lenharth, A., Adve, V., King, S.T.: Recovery domains: An organizing principle for recoverable operating systems. In: ACM Conf. Architectural Support for Programming Languages and Operating Systems (March 2009)

    Google Scholar 

  22. Locasto, M.E., Stavrou, A., Cretu, G.F., Keromytis, A.D.: From STEM to SEAD: Speculative execution for automated defense. In: USENIX Annual Tech. Conf. (June 2007)

    Google Scholar 

  23. Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: LogTM: Log-based transactional memory. In: IEEE Symp. High Perf. Comp. Arch. (February 2006)

    Google Scholar 

  24. Stonebraker, M.: Implementation of integrity constraints and views by query modification. In: ACM SIGMOD (1975)

    Google Scholar 

  25. Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., Gupta, A.: The SPLASH-2 programs: Characterization and methodological considerations. In: Intl. Symp. on Comp. Arch. (June 1995)

    Google Scholar 

  26. Yen, L., Bobba, J., Marty, M.R., Moore, K.E., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: LogTM-SE: Decoupling hardware transactional memory from caches. In: IEEE Symp. High Perf. Comp. Arch. (February 2007)

    Google Scholar 

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Butt, S., Ganapathy, V., Baliga, A., Christodorescu, M. (2012). Monitoring Data Structures Using Hardware Transactional Memory. In: Khurshid, S., Sen, K. (eds) Runtime Verification. RV 2011. Lecture Notes in Computer Science, vol 7186. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-29860-8_26

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  • DOI: https://doi.org/10.1007/978-3-642-29860-8_26

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-29859-2

  • Online ISBN: 978-3-642-29860-8

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