Abstract
A new CMOS Analog Multiplier in Current Domain using very negligible amount of static power is presented. This circuit uses the concept of harmonics along with the square law of current in a saturated MOS and is simulated using 90nm Technology Node of UMC. The supply voltage Vdd is kept at +1V. The circuit, when drawn using the Cadence Virtuoso Schematic Editor and simulated using the Spectre Simulator, gave a -3dB bandwidth of 2.07GHz with a load capacitance of 10fF.
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References
Li, S.C., Cha, J.C.: 0.5V- +.I5 V VHF CMOS LV/LP Four-Quadrant Analog Multiplier in Modified Bridged-Triode Scheme. In: Proceedings of the 2002 International Symposium on Low Power Electronics and Design, ISLPED 2002, pp. 227–232 (2002)
Sawigun, C., Mahattanakul, J.: A 1.5V, Wide-Input Range, High-Bandwidth, CMOS Four-Quadrant Analog Multiplier. In: IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp. 2318–2321 (2008), doi:10.1109/ISCAS.2008.4541918
Al-Nsour, M., Abdel-Aty-Zohdy, H.S.: A Wide Input Range Analog Multiplier For Neuro-computing. In: Proceedings of the 40th Midwest Symposium on Circuits and Systems, vol. 1, pp. 13–16 (1997), doi:10.1109/MWSCAS.1997.666022
Hidayat, R., Dejhan, K., Moungnoul, P., Miyanaga, Y.: OTA-Based High Frequency CMOS Multiplier and Squaring Circuit. In: International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2008, pp. 1–4 (2009), doi:10.1109/ISPACS.2009.4806748
Prommee, P., Somdunyakanok, M., Kumngern, M., Dejhan, K.: Single Low-Supply Current-mode CMOS Analog Multiplier Circuit. In: International Symposium on Communications and Information Technologies, ISCIT 2006, pp. 1101–1104 (2006), doi:10.1109/ISCIT.2006.339949
Mahmoud, S.A.: CMOS Fully Differential CMOS Four-Quadrant Analog Multiplier. In: International Conference on Microelectronics, ICM 2008, pp. 27–30 (2008), doi:10.1109/ICM.2008.5393543
Li, S.C.: A Very-High-Frequency CMOS Four-Quadrant Analogue Multiplier. In: Proceedings of 1997 IEEE International Symposium on Circuits and Systems, ISCAS 1997, vol. 1, pp. 233–236 (1997), doi:10.1109/ISCAS.1997.608681
Ramirez-Angulo, J., Carvajal, R.G., Martinez-Heredia, J.: 1.4V Supply, Wide Swing, High Frequency CMOS Analogue Multiplier with High Current Efficiency. In: Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, ISCAS 2000 Geneva, vol. 5, pp. 533–536 (2000), doi:10.1109/ISCAS.2000.857489
Diwakar, K., Senthilpari, C., Singh, A.K., Soong, L.W.: Analog Multiplier with High Accuracy. In: First International Conference on Computational Intelligence, Communication Systems and Networks, CICSYN 2009, pp. 62–66 (2009), doi:10.1109/CICSYN.2009.10
Ghanavati, B., Nowbakht, A.: + 1V high frequency four quadrant current Multiplier. Electronics Letters 46(14), 974–976 (2010), doi:10.1049/el.2010.1020
Chen, C., Li, Z.: A low-power CMOS analog multiplier. IEEE Transactions on Circuits and Systems II: Express Briefs 53(2), 100–104 (2006), doi:10.1109/TCSII.2005.857089
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Gupta, A., Sarkar, S. (2012). An Efficient High Frequency and Low Power Analog Multiplier in Current Domain. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_1
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DOI: https://doi.org/10.1007/978-3-642-31494-0_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
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