Abstract
With the scaling of technology node and voltage levels, VLSI circuits are facing the challenge of tolerance to soft errors normally caused by alpha particle or neutron hits. These radiation strikes, resulting into bit upsets referred to as single-event upsets (SEUs), may be catastrophic in few sensitive applications and severely undermine the quality and reliability in other applications. In this paper we propose two novel SEU tolerant latch designs RHL-A and RHL-B. Our latch designs are area efficient in comparison with the earlier proposals. Simulation results show that the proposed latch designs is extremely robust as it does not flip even for a transient pulse with 58 times the Qcrit of a standard latch cell. Compared to standard latch, RHL-A uses 40 percent more transistors and is 65 percent slower, whereas RHL-B uses 60 percent more transistors but is 65 percent faster.
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Shayan, M., Singh, V., Singh, A.D., Fujita, M. (2012). SEU Tolerant Robust Latch Design. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_26
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DOI: https://doi.org/10.1007/978-3-642-31494-0_26
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