Abstract
Network-on-chip (NoC) is the most effective communication structure for System-on-Chip (SoC) components. Test data compression is essential to reduce test data volume, to decreases test costs. In this paper, a test compression and decompression solution is proposed based on binary arithmetic operations. Experimental results for full scan test data set of ISCAS’89 benchmarks are demonstrated. The major advantages include high compression ratio and a low cost decoder. It is observed that the proposed compression method achieves a compression ratio as high as 93.56% for ISCAS’89 benchmarks.
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Chaki, S., Giri, C. (2012). Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_38
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DOI: https://doi.org/10.1007/978-3-642-31494-0_38
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
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