Abstract
Recent wireless communication standards such as 3GPP-LTE, WiMax, DVB-SH and HSPA incorporates turbo code for its excellent coding performance. The interleavers involved in these turbo encoder and decoder play vital role in their performance. In this paper, we have proposed a linear feedback shift register (LFSR) based interleaver for turbo code. The proposed interleaver is compared with existing quadratic permutation polynomial (QPP) and almost regular permutation (ARP) interleavers. The investigation on the hardware implementation of these interleavers were carried out in terms of area and power consumption, and maximum frequency of operation. Hardware implementations were performed in Field Programmable Gate Array (FPGA), as well as in Application Specific Integrated Circuit (ASIC) using 130 nm complementary metal oxide semiconductor (CMOS) technology.
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Shrestha, R., Paily, R. (2012). Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_4
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DOI: https://doi.org/10.1007/978-3-642-31494-0_4
Publisher Name: Springer, Berlin, Heidelberg
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