Abstract
A physical synthesis flow for data path circuits is proposed that integrates bit-slice tiling and gate size selection in traditional P&R tool, which outperforms traditional P&R tool in power and timing. This approach also reduces effort and multiple iterations of manual flow.
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References
Leveugle, R., Safinia, C., Magarshack, P., Sponga, L.: Data path implementation: bit-slice structure versus standard cells. In: Proc. of Euro ASIC 1992, pp. 83–88 (1992)
Ienne, P., Griessing, A.: Practical experiences with standard cell based data path design tools. Do we really need regular layouts? In: Proc. of DAC, pp. 396–401 (1998)
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© 2012 Springer-Verlag Berlin Heidelberg
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Saun, V.S., Chatterjee, S., Arunachalam, A. (2012). Integrated Placement and Optimization Flow for Structured and Regular Logic. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_41
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DOI: https://doi.org/10.1007/978-3-642-31494-0_41
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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