Abstract
In this paper, an efficient Montgomery modular multiplier is designed exploiting the efficiency of inbuilt multiplier and adder soft-cores of DSP blocks. 256×256 bit multiplier has been implemented with (i) fully parallel, (ii) pipelined and (iii) semi parallel architectures that consumes upto 16 DSP48E1 64×64 bit soft-cores provided by Xilinx 12.4 ISE Design Suite. Performances with respect to area, operating frequency and design latency have been compared.
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References
Huang, G., El-Ghazawi: New Hardware Architectures for Montgomery Modular Multiplication Algorithm. IEEE Transactions on Computers, 923–936 (2011)
Montgomery, P.: Modular multiplication without trial division. Mathematics of Computation 44(170), 519–521 (1985)
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Mondal, A., Ghosh, S., Das, A., Chowdhury, D.R. (2012). Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_47
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DOI: https://doi.org/10.1007/978-3-642-31494-0_47
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
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