Comparative Study and Analysis of Short Channel Effects for 180nm and 45nm Transistors

Abstract

There has been a continuous scaling trend of semiconductor devices in order to keep pace with Moore’s law and this seems to an end. This is due to various design pitfalls like short channel effects (SCE) and variations in process design parameters leading to high leakage currents. The design of low power circuits, battery operated and portable electronic systems has become a challenge for the VLSI circuit designers with scaling trends. The recent venture by Intel in silicon material processes technology, in the manufacture of 45nm Metal Oxide semiconductor Field Effect Transistor (MOSFET) has extended Moore’s Law for some more years. Circuit designing using MOSFETs at deep sub micron levels, needs a careful study of the behaviour of short channel devices for the parameter variations such as threshold voltage, channel length leading to high leakage currents and poor performance of devices. The possibility of scaling down of transistors further has been achieved by replacement of silicon oxide with high-k dielectric gate material by Intel in 45nm devices [1, 2]. In this paper an attempt has been made to investigate and compare the short channel effects and other design challenges for 180nm and 45 nm technology nodes. Thus, this paper presents a comparative study of 180nm and 45nm nMOS transistors with respect to short channel effects and its impact on CMOS circuit design parameters. The results of extensive simulations have been presented and were carried out using Virtuoso Cadence Spectre Simulator.