Abstract
Growing power consumption and communication delay are motivating architectural features that disclose on-chip communication to a compiler. Coarse grained reconfigurable architectures (CGRAs) are one example of communication disclosed architectures. In these architectures, the compiler forms dataflow graphs that specify how the architecture executions instruction codes on its processing elements.
In this work, we propose an energy efficient algorithm that performs automatically mapping applications onto a CGRA. We design the code mapping algorithm with two heuristics: (1) critical path estimates, and (2) data path proximity in processing elements of a CGRA. We use a greedy based approach to explore possible mappings and to find an optimal mapping on a CGRA. We show that the proposed algorithm achieves near optimal quality mappings for all multimedia kernel codes.
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© 2012 Springer-Verlag Berlin Heidelberg
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Youn, J., Cho, D. (2012). A Delay and Distance Aware Code Mapping Technique for Coarse-Grained Reconfigurable Array Processors. In: Lee, G., Howard, D., Ślęzak, D., Hong, Y.S. (eds) Convergence and Hybrid Information Technology. ICHIT 2012. Communications in Computer and Information Science, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32692-9_61
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DOI: https://doi.org/10.1007/978-3-642-32692-9_61
Publisher Name: Springer, Berlin, Heidelberg
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