Abstract
The Wishbone System-on-Chip bus protocol, which is developed by the Silicore Corporation, in connection with its characteristics and complexity, it is verified by the model checking approach. Firstly, the communication model of IP cores is created, and a FSM modeling approach for the model is proposed. Secondly, the non-starvation and fairness properties are specified using the computation tree logic. Finally these properties are verified against the model with the help of the model checking tool SMV. The result shows that there is a bus starvation scenario which will be caused by the unfairness of arbiter. This research demonstrates that there are some flaws with the specification of Wishbone System-on-Chip bus protocol. It also reflects that the arbitration mechanism is prone to flaw and therefore the formal modeling and verification is necessary.
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References
ARM. Advanced microcontroller bus architecture specification [S/OL] (1999), http://www.arm.com/armtech/AMBA_spec
IBM. 32-bit processor local bus architecture specifications [S/OL], Version 2.9., http://www.ibm.com/chips/products/coreconnect/
Open-Core Protocol Int. Partnership Association Inc. Open-core protocol specification [S/OL], Release 1.0 (2001), http://www.ocpip.org
WISHBONE, Revision B.3 Specification [S/OL], http://www.opencores.org/-projects.cgi/web/wishbone/wishbone
Roychoudhury, A., Mitra, T., Karri, S.R.: Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol. In: The Design, Automation, and Test Europe Conference, Munich, Germany, pp. 828–833 (March 2003)
Chauhan, P., Clarke, E.M., Lu, Y., Wang, D.: Verifying IP-Core based System-On-Chip Designs. In: The IEEE International AS IC/SOC Conference, pp. 27–31 (September 1999)
Goel, A., Lee, W.R.: Formal verification of an IBM CoreConnect processor local bus arbiter core. In: DAC 2000, pp. 196–200 (2000)
Lin, H.-M., Yen, C.-C., Shih, C.-H., Jou, J.-Y.: On compliance test of on-chip bus for SOC. In: ASP-DAC 2004, pp. 328–333 (2004)
Clarke, E.M., Emerson, E.A., Sistla, A.P.: Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Transactions on Programming Languages and Systems 8(2), 244–263 (1986)
McMillan, K.L.: Symbolic Model Checking: An Approach to the State Explosion Problem. Carnegie-Mellon University publication CMU-CS-92-131 (May 1992)
Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE Transactions on Computers C-35(8) (1986)
Cadence Berkeley Laboratories, California, USA. The SMV Model Checker (1999), http://www-cad.eecs.berkeley.edu/kenmcmil/smv/
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Luo, R., Tan, H. (2012). Formal Modeling and Model Checking Analysis of the Wishbone System-on-Chip Bus Protocol. In: Liu, B., Ma, M., Chang, J. (eds) Information Computing and Applications. ICICA 2012. Lecture Notes in Computer Science, vol 7473. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34062-8_28
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DOI: https://doi.org/10.1007/978-3-642-34062-8_28
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