A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier

Abstract

In this paper, a hardware implementation of MSB-first word-parallel bit-serial multiplier with shorter delay time than other existing multipliers in finite field is presented. The proposed multiplier operates in polynomial basis of GF(2^m). This multiplier is of serial type, i.e., after receiving the coordinates of the two input field elements, it goes through w, 1(w(m, iterations (i.e. clock cycles) to finally yield all the coordinates of the product in parallel. The value of w is the selected word size. The word-parallel bit-serial multiplier is faster than bit-serial multipliers and has lower hardware area complexity than bit-parallel multipliers. Therefore, the most significant feature of the proposed multiplier is a proper trade-off between hardware complexity and delay time.