Skip to main content
SpringerLink
Log in

HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs

  • Conference paper
Reconfigurable Computing: Architectures, Tools and Applications (ARC 2013)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 7806))

Included in the following conference series:

Abstract

Partial reconfiguration (PR) enables shared FPGA systems to nonintrusively time multiplex hardware tasks in partially reconfigurable regions (PRRs). To fully exploit PR, higher priority tasks should preempt lower priority tasks and preempted tasks should resume execution in any PRR. This preemption/ resumption requires saving/restoring the preempted task’s execution context and relocating the task to another PRR, however, prior works only provide partial solutions and impose limitations and/or overheads. We propose on-chip hardware task relocation (HTR) software, which enables a task’s execution state to be saved, relocated to, and restored in any PRR with sufficient resources. The HTR software executes on a soft-core processor in the FPGA’s static region, and is thus portable across any system/application. Experimental results evaluate HTR execution times, enabling designers to tradeoff task/PRR granularity and HTR execution times based on application requirements.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 49.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Becker, T., Koester, M., Luk, W.: Automated placement of reconfigurable regions for relocatable modules. In: Proc. of the 2010 IEEE Intl. Symp. on Circuits and Systems (ISCAS 2010), Paris, France, pp. 3341–3344 (2010)

    Google Scholar 

  2. Becker, T., Luk, W., Cheung, P.Y.K.: Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. In: 15th Annual IEEE Symp. on Field-Programmable Custom Machines (FCCM 2007), Napa, California, pp. 35–44 (2007)

    Google Scholar 

  3. Blodget, B., James-Roxby, P., Keller, E., McMillan, S., Sundararajan, P.: A Self-Reconfiguring Platform. In: Cheung, P.Y.K., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 565–574. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  4. Carver, J., Pittman, N., Forin, A.: Relocation and Automatic Floor-planning of FPGA Partial Configuration Bitstreams. Microsoft Research, WA. Technical Report MSR-TR-2008-111, Redmond, Washington (2008)

    Google Scholar 

  5. Corbetta, S., Morandi, M., Novati, M., Santambrogio, M.D., Sciuto, D., Spoletini, P.: Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration. IEEE Trans. on Very Large Scale Integration (VLSI) Systems 17(11), 1650–1654 (2009)

    Article  Google Scholar 

  6. Flynn, A., Gordon-Ross, A., George, A.D.: Bitstream Relocation with Local Clock Domains for Partially Reconfigurable FPGAs. In: Design, Automation & Test in Europe Conference & Exhibition 2009 (DATE 2009), Nice, France, pp. 300–303 (2009)

    Google Scholar 

  7. Horta, E.L., Lockwood, J.W.: PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs). Technical Report WUCS-01-13, Washington University, St. Louis, Missouri (2001)

    Google Scholar 

  8. Jovanovic, S., Tanougast, C., Weber, S.: A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable Systems. In: 2nd NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), Edinburgh, United Kingdom, pp. 358–364 (2007)

    Google Scholar 

  9. Jozwik, K., Tomiyama, H., Honda, S., Takada, H.: A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. In: Intl. Conf. on Field Programmable Logic and Applications (FPL 2010), Milano, Italy, pp. 352–255 (2010)

    Google Scholar 

  10. Kalte, H., Lee, G., Porrmann, M., Rückert, U.: REPLICA: A Bitstream Manipulation Filter for Module Relocation in Partial Reconfigurable Systems. In: Proc. of the 19th IEEE Intl. Parallel and Distributed Processing Symp. (IPDPS 2005), Denver, Colorado (2005)

    Google Scholar 

  11. Kalte, H., Porrmann, M.: Context Saving and Restoring for Multitasking in Reconfigurable Systems. In: Intl. Conf. on Field Programmable Logic and Applications (FPL 2005), Tampere, Finland, pp. 223–228 (2005)

    Google Scholar 

  12. Kalte, H., Porrmann, M.: REPLICA2Pro: Task Relocation by Bitstream Manipulation in Virtex-II/Pro FPGAs. In: Proc. of the 3rd Conf. on Computing Frontiers (CF 2006), pp. 403–412. ACM, New York (2006)

    Chapter  Google Scholar 

  13. Koch, D., Haubelt, C., Teich, J.: Efficient Hardware Checkpointing: Concepts, Overhead Analysis, and Implementation. In: Proc. of the ACM/SIGDA 15th Intl. Symp. on Field Programmable Gate Arrays (FPGA 2007), pp. 188–196. ACM, New York (2007)

    Chapter  Google Scholar 

  14. Koester, M., Porrmann, M., Kalte, H.: Relocation and Defragmentation for Heterogeneous Reconfigurable Systems. In: Proc. of Intl. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA 2006), pp. 70–76. Las Vegas, Nevada (2006)

    Google Scholar 

  15. Landaker, W.J., Wirthlin, M.J., Hutchings, B.L.: Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, pp. 806–815. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  16. Santambrogio, M.D., Cancare, F., Cattaneo, R., Bhandari, S., Sciuto, D.: An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems. In: 2012 IEEE 26th International Symposium on Parallel & Distributed Processing, Workshop and PhD Forum (IPDPSW 2012), Shangai, China, pp. 336–343 (2012)

    Google Scholar 

  17. Simmler, H., Levinson, L., Männer, R.: Multitasking on FPGA Coprocessors. In: Grünbacher, H., Hartenstein, R.W. (eds.) FPL 2000. LNCS, vol. 1896, pp. 121–130. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  18. Sudarsanam, A., Kallam, R., Dasu, A.: PRR-PRR Dynamic Relocation. IEEE Computer Architecture Letters 8(2), 44–47 (2009)

    Article  Google Scholar 

  19. Xilinx, Inc.: Virtex-5 FPGA Configuration User Guide v3.10 (UG191) (November 18, 2011)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. NSF Center for High-Performance Reconfigurable Computing (CHREC), Dept. of Electrical and Computer Engineering, University of Florida, Gainesville, FL, 32611, USA

    Aurelio Morales-Villanueva & Ann Gordon-Ross

Authors
  1. Aurelio Morales-Villanueva
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ann Gordon-Ross
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, University of California, 92521, Riverside, CA, USA

    Philip Brisk

  2. Department of Computing, Imperial College, SW7 2AZ, London, UK

    José Gabriel de Figueiredo Coutinho

  3. Departamento de Engenharia Informática, Instituto Superior Técnico/INESC-ID, Av. Prof. Dr. Cavaco Silva, 2780-990, Porto Salvo, Portugal

    Pedro C. Diniz

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Morales-Villanueva, A., Gordon-Ross, A. (2013). HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs. In: Brisk, P., de Figueiredo Coutinho, J.G., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2013. Lecture Notes in Computer Science, vol 7806. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36812-7_18

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-36812-7_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36811-0

  • Online ISBN: 978-3-642-36812-7

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation