Abstract
Coarse-grained reconfigurable array (CGRA) is a competitive hardware platform for computation intensive tasks in many application domains. The performance of CGRA heavily depends on the mapping algorithm which exploits different level of parallelisms. Unfortunately, the mapping problem on CGRA is proved to be NP-complete. In this paper, we propose a genetic based modulo scheduling algorithm to map application kernels onto CGRA. An efficient routing heuristic is also presented to reduce the mapping time. Experiment result shows our algorithm outperforms other heuristic algorithms both in solution’s quality and mapping time.
Keywords
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Zain ul A, Svensson B (2009) Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing. Microprocess Microsyst 33:161–178
Shields CO Jr (2001) Area efficient layouts of binary trees in grids. Ph.D. thesis, The University of Texas at Dallas
Mei B, Vernalde S, Verkest D, De Man H, Lauwereins R (2002) DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. In: Proceedings of international conference on field-programmable technology, FPT, pp 166–173
Park H, Fan K, Mahlke SA, Oh T, Kim H (2008) Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. In: Proceedings of the international conference on parallel architectures and compilation techniques, PACT, pp 166–176
Back T, Hammel U, Schwefel H-P (1997) Evolutionary computation: comments on the history and current state. IEEE Trans Evol Comput 1(1):3–17
Hwang C-T, Lee J-H, Hsu Y-C (1991) A formal approach to the scheduling problem in high level synthesis. IEEE Trans Comput Aided Des Integr Circuits Syst 10(14):464–475
Elghazali M, Areibi S, Grewal G, Erb A, Spenceley J (2009) A comparison of hardware acceleration methods for VLSI maze routing. In: Proceedings of IEEE toronto international conference on science and technology for humanity (TIC-STH), pp 563–568
Ramakrishna Rau B (1994) Iterative module scheduling: an algorithm for software pipelining loops. In: Proceedings of the 27th annual international symposium on microarchitecture, pp 63–74
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Zhou, L., Liu, D., Tang, M., Liu, H. (2013). Mapping Loops onto Coarse-Grained Reconfigurable Array Using Genetic Algorithm. In: Yin, Z., Pan, L., Fang, X. (eds) Proceedings of The Eighth International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA), 2013. Advances in Intelligent Systems and Computing, vol 212. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-37502-6_95
Download citation
DOI: https://doi.org/10.1007/978-3-642-37502-6_95
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-37501-9
Online ISBN: 978-3-642-37502-6
eBook Packages: EngineeringEngineering (R0)