Abstract
This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of DES, TDES and AES cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of architecture. Clock gating technique is used to reduce the power consumption in MIPS crypto processor. This approach results in processor that meets power consumption and performance specification for security applications. Proposed design Implementation concludes higher system performance and reducing gate propagation delay while reducing operating power consumption. The purpose this processor is to find the maximum clock frequency and adjusted setup and hold time based on propagation delay for circuits with combinational and sequential gates. Testing results shows that the MIPS crypto processor operates successfully at a working frequency of DES, TDES & AES crypto processor at 218MHz, 209MHz, & 210MHz and a operating bandwidth of 664Mbits/s, 636Mbits/s, and 560Mbits/s.
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© 2013 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Singh, K.P., Parmar, S., Kumar, D. (2013). Design of High Performance MIPS Cryptography Processor. In: Singh, K., Awasthi, A.K. (eds) Quality, Reliability, Security and Robustness in Heterogeneous Networks. QShine 2013. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 115. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-37949-9_68
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DOI: https://doi.org/10.1007/978-3-642-37949-9_68
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