Using Interleaving to Avoid the Effects of Multiple Adjacent Faults in On-Chip Interconnection Lines

Abstract

As technology shrinks, higher operating frequencies, reduced feature sizes and lower supply voltages allow greater performance, but the reliability has been affected negatively. Smaller devices and wire spacing lead to an increase in the occurrence of multiple adjacent faults. Thus, the system reliability is seriously affected. Error correction codes are a powerful technique that allows higher reliability using information redundancy. This paper focuses on the use of interleaved codes to tolerate faults in on-chip interconnection lines. Interleaving has been extensively used in memories, but not in system buses. To illustrate the features of this technique, an example has been included.