Abstract
This paper presents a Boolean SAT constraint satisfaction formulation of the detailed placement problem for programmable logic. The detailed placement problem is usually considered a poor candidate for a SAT-based solution due to complex timing constraints and the large size of the problem space. To overcome these challenges, we encode domain-specific knowledge into the problem formulation and add new features to the SAT solver. First, a Boolean encoding of timing constraints is presented that utilizes concepts from static timing analysis. Second, future cost clauses are added to the formulation to guide the SAT solver in a manner similar to A* search. Third, a dynamic clause generation approach is described that keeps the working problem size small by adding clauses on demand as the SAT solver explores the problem space. This includes dynamic cardinality clauses and dynamic addition of literals to cardinality clauses.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Bacchus, F.: Enhancing Davis Putnam with extended binary clause reasoning. In: National Conference on Artificial Intelligence, pp. 613–619 (July 2002)
Betz, V., Rose, J.: VPR: A new packing, placement, and routing tool for FPGA research. In: Glesner, M., Luk, W. (eds.) FPL 1997. LNCS, vol. 1304, pp. 213–222. Springer, Heidelberg (1997)
Chen, D., Cong, J., Pan, P.: FPGA design automation: A survey. Foundations and Trends in Electronic Design Automation 1(3), 195–330 (2006)
Devadas, S.: Optimal layout via Boolean satisfiability. In: IEEE International Conference on Computer-Aided Design, pp. 294–297 (November 1989)
Drechsler, R., Eggersglüß, S., Fey, G., Tille, D.: Test Pattern Generation using Boolean Proof Engines. Springer (2009)
Eén, N., Sörensson, N.: An extensible SAT-solver. In: Giunchiglia, E., Tacchella, A. (eds.) SAT 2003. LNCS, vol. 2919, pp. 502–518. Springer, Heidelberg (2004)
Eén, N., Sörensson, N.: Temporal induction by incremental SAT solving. In: First Intl. Workshop on Bounded Model Checking, vol. 89, pp. 543–560 (2003)
Ganesh, V., O’Donnell, C.W., Soos, M., Devadas, S., Rinard, M.C., Solar-Lezama, A.: Lynx: A programmatic SAT solver for the RNA-folding problem. In: Cimatti, A., Sebastiani, R. (eds.) SAT 2012. LNCS, vol. 7317, pp. 143–156. Springer, Heidelberg (2012)
Kirkpatrick, T.I., Clark, N.R.: PERT as an aid to logic design. IBM Journal of Research and Development 10(2), 135–141 (1966)
Kuehlmann, A., Paruthi, V., Krohm, F., Ganai, M.: Robust Boolean reasoning for equivalence checking and functional property verification. IEEE Transactions on Computer-Aided Design 21(12), 1377–1394 (2002)
Kuehlmann, A.: Dynamic transition relation simplification for bounded property checking. In: International Conference on Computer-Aided Design, pp. 50–57 (2004)
Kuon, I., Tessier, R., Rose, J.: FPGA architecture: Survey and challenges. Foundations and Trends in Electronic Design Automation 2(2), 135–253 (2008)
Liffiton, M.H., Maglalang, J.C.: A cardinality solver: More expressive constraints for free. In: Cimatti, A., Sebastiani, R. (eds.) SAT 2012. LNCS, vol. 7317, pp. 485–486. Springer, Heidelberg (2012)
Mishchenko, A., Brayton, R., Jiang, J.R., Jang, S.: SAT-based logic optimization and resynthesis. In: Intl. Workshop on Logic and Synthesis, pp. 358–364 (May 2007)
Moskewicz, M., Madigan, C., Zhao, Y., Zhang, L., Malik, S.: Chaff: Engineering an efficient SAT solver. In: Design Automation Conference, pp. 530–535 (2001)
Nam, G., Aloul, F., Sakallah, K., Rutenbar, R.: A comparative study of two Boolean formulations of FPGA detailed routing constraints. IEEE Transactions on Computers 53(6) (June 2004)
Nam, G., Sakallah, K., Rutenbar, R.: Satisfiability-based layout revisited: Detailed routing of complex FPGAs via search-based Boolean SAT. In: Intl. Symposium on Field Programmable Gate Arrays, pp. 167–175 (1999)
Ohrimenko, O., Stuckey, P., Codish, M.: Propagation via lazy clause generation. Constraints 14(3), 357–391 (2009)
Seshia, S.: Adaptive Eager Boolean Encoding for Arithmetic Reasoning in Verification. PhD thesis, Carnegie Mellon University (2005)
Various. OpenCores open source hardware IP cores (April 2013), http://opencores.org
Glenn Wood, R., Rutenbar, R.: FPGA routing and routability estimation via Boolean satisfiability. IEEE Transactions on VLSI 6(2) (June 1998)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mihal, A., Teig, S. (2013). A Constraint Satisfaction Approach for Programmable Logic Detailed Placement. In: Järvisalo, M., Van Gelder, A. (eds) Theory and Applications of Satisfiability Testing – SAT 2013. SAT 2013. Lecture Notes in Computer Science, vol 7962. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-39071-5_16
Download citation
DOI: https://doi.org/10.1007/978-3-642-39071-5_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-39070-8
Online ISBN: 978-3-642-39071-5
eBook Packages: Computer ScienceComputer Science (R0)