Abstract
Network-on-Chip (NoC) has evolved as a promising technique for the present-day’s communication in the VLSI design paradigm. It ensures reusability, parallelism and scalability. To reduce the testing cost of such a system, the existing communication structure ca be reused. In this paper, we have proposed a Particle Swarm Optimization (PSO) based mixed test scheduling approach to test the cores in the NoC environment. It incorporates both non-preemptive and preemptive tests. Experimental results for ITC’02 System-on-Chip (SoC) benchmarks show that the PSO based mixed test scheduling approach efficiently reduces the overall test application time compared to other existing works.
This work is partially supported by Department of Information and Technology, Govt. of India (9(5)/2010-MDD), Dated 23/11/2011.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Iyenger, V., Chakrabatry, K.: System-on-a-Chip Test Scheduling With Precedence Relationships, Preemption and Power Constraints. IEEE Trans. on Computer-aided Design of Integrated Circuit and Systems 21(9), 1088–1094 (2002)
Cota, E., Liu, C.: Constrain-Driven Test scheduling for NoC-Based Systems. IEEE Trans. on Computer-Aided Design of Integrated Circuit and Systems 25(11), 2465–2478 (2006)
Manna, K., Khaitan, P., Chattopadhyay, S., Sengupta, I.: Particle Swarm Optimization based Technique for Network-on-Chip Testing. In: Proceedings of IEEE Intl. Conf. EAIT, pp. 66–69 (2012)
Iyengar, V., Chakrabarty, K.: Test wrapper and test access mechanism co-optimization for system-on-chip. Journal of Electronic Testing: Theory and Appl. 18, 213–230 (2002)
Marinissen, E.J., Iyengar, V., Chakrabarty, K.: A Set of Benchmarks for Modular Testing of SOCs. In: Proceedings of International Test Conference, pp. 519–528 (2002)
Liu, C., Cota, E., Sharif, H., Pradhan, D.K.: Test scheduling for Network-on-Chip with BIST and precedence constraints. In: Proceedings of International Test Conference, pp. 1369–1378.
Kundu, S., Sathi, M., Chattopadhyay, S.: Genetic Algorithm based Test Scheduling for Network-on-Chip. In: Procedings of IEEE VLSI Design and Test Symposium (2007)
Zou, W., Reddy, S.M., Pomeranz, I., Huang, Y.: SoC Test Scheduling Using Simulated Annealing. In: Procedings of IEEE VLSI Test Symposium (VTS 2003), pp. 325–330 (2003)
Farah, R., Harmanani, H.: A method for efficient NoC test scheduling using deterministic routing. In: Proceedings of IEEE International SOC Conference (SOCC), pp. 363–366 (2010)
Ahn, J., Kang, S.: Noc-based soc test scheduling using ant colony optimization. ETRI Journal 30, 129–140 (2008)
Salamy, H., Harmanani, H.M.: An optimal formulation for test scheduling network-on-chip using multiple clock rates. In: Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 215–218 (2011)
Cota, E., Carro, L., Wagner, F., Lubaszewski, M.: Power-aware noc reuse on the testing of core-based systems. In: Proceedings of International Test Conference, pp. 612–621 (2003)
Rosinger, P., Al-Hasmi, B.M., Chakrabarty, K.: Thermal-safe Test Scheduling for Core-Based System-on-Chip Integrated Circuit. IEEE Trans. on Computer-aided Design of Integrated Circuit and Systems 25(11), 2502–2512 (2006)
Liu, C., Iyengar, V., Pradhan, D.K.: Thermal-aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. In: Proceedings of VLSI Test Symposium, pp. 46–51 (2006)
He, Z.,, Z.: A heuristic for thermal-safe SoC test scheduling. In: Proceedings of International Test Conference, pp. 1–10 (2007)
Yao, C., Saluja, K.K., Ramanathan, P.: Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. IEEE Trans. on Computer-aided Design of Integrated Circuit and Systems 30(2), 317–322 (2011)
Kennedy, I., Eberhart, R.C.: Particle Swarm Optimization. In: Proceedings of IEEE International Conference on Neural Networks, NJ, pp. 1942–1948 (1995)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Manna, K., Singh, S., Chattopadhyay, S., Sengupta, I. (2013). Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_10
Download citation
DOI: https://doi.org/10.1007/978-3-642-42024-5_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
eBook Packages: Computer ScienceComputer Science (R0)