Abstract
This paper presents an improved g m /I D methodology for the design of low-power CMOS operational transconductance amplifier (OTA) circuit using nano-scale CMOS technology. This methodology takes into considerations the dependence of the Early voltage parameter with the bias points of a nano-scale MOS transistor. With such considerations, the DC voltage gain of the circuit can be controlled by adjusting the bias points of the transistors and keeping the channel length constant. The advantage of the improved methodology over the traditional methodology has been discussed and illustrated with simulation results.
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© 2013 Springer-Verlag Berlin Heidelberg
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Paul, S., Dana, A., Pandit, S. (2013). An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_16
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DOI: https://doi.org/10.1007/978-3-642-42024-5_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
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