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Defect Diagnosis of Digital Circuits Using Surrogate Faults

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VLSI Design and Test

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 382))

Abstract

Classical single stuck-at faults are analyzed as surrogates for any non-classical fault that may have caused an observed failure. Although multiple stuck-at faults are used as an illustrative example of non-classical faults, proposed algorithms are applicable to any other type of fault. Our effect-cause analysis is less complex than existing methods. The diagnostic procedure adds or removes faults from a set of candidate faults based on the observed circuit outputs, using minimal fault simulation, to obtain a small set of suspected faults.

Research supported in part by the National Science Foundation Grant CCF-1116213.

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References

  1. ATPG and Failure Diagnosis Tools. Mentor Graphics Corp., Wilsonville, OR (2009)

    Google Scholar 

  2. Python Tutorial Release 2.6.3. docs@python.org. Python Software Foundation (2009)

    Google Scholar 

  3. Abramovici, M., Breuer, M.A.: Fault Diagnosis Based on Effect-Cause Analysis: An Introduction. In: Proc. 17th Design Automation Conf., pp. 69–76 (June 1980)

    Google Scholar 

  4. Abramovici, M., Breuer, M.A.: Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. IEEE Transactions on Computers C-29(6), 451–460 (1980)

    Article  MathSciNet  Google Scholar 

  5. Agrawal, V.D., Baik, D.H., Kim, Y.C., Saluja, K.K.: Exclusive Test and Its Applications to Fault Diagnosis. In: Proc. 16th International Conf. VLSI Design, pp. 143–148 (2003)

    Google Scholar 

  6. Alagappan, C.: Dictionary-Less Defect Diagnosis as Real or Surrogate Single Stuck-At Faults. Master’s thesis, Auburn University, Auburn, Alabama (May 2013)

    Google Scholar 

  7. Beckler, M., Blanton, R.D.(S.): On-Chip Diagnosis for Early-Life and Wear-Out Failures. In: Proc. International Test. Conf., pp. 1–10 (November 2012)

    Google Scholar 

  8. Bushnell, M.L., Agrawal, V.D.: Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. Springer, Boston (2000)

    Google Scholar 

  9. Cox, H., Rajski, J.: A Method of Fault Analysis for Test Generation and Fault Diagnosis. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 7(7), 813–833 (1988)

    Article  Google Scholar 

  10. Grimaila, M.R., Lee, S., Dworak, J., Butler, K.M., Stewart, B., Houchins, B., Mathur, V., Park, J., Wang, L.-C., Mercer, M.R.: REDO - Random Excitation and Deterministic Observation - First Commercial Experiment. In: Proc. 17th IEEE VLSI Test Symp., pp. 268–274 (April 1999)

    Google Scholar 

  11. Kofler, M.: Definitive Guide to Excel VBA. Apress, New York (2000)

    Book  Google Scholar 

  12. Millman, S.D., McCluskey, E.J., Acken, J.M.: Diagnosing CMOS Bridging Faults With Stuck-At Fault Dictionaries. In: Proc. International Test. Conf., pp. 860–870 (September 1990)

    Google Scholar 

  13. Reddy, S.M., Pomeranz, I., Kajihara, S.: On the Effects of Test Compaction on Defect Coverage. In: Proc. 14th IEEE VLSI Test Symp., pp. 430–435 (April 1996)

    Google Scholar 

  14. Stroud, C.E.: A Designer’s Guide to Built-in Self-Test. Springer, Boston (2002)

    Google Scholar 

  15. Venkataraman, S., Drummonds, S.B.: POIROT: A Logic Fault Diagnosis Tool and Its Applications. In: Proc. International Test Conf., pp. 253–262 (2000)

    Google Scholar 

  16. Wang, L.C., Williams, T.W., Mercer, M.R.: On Efficiently and Reliably Achieving Low Defective Part Levels. In: Proc. International Test Conf., pp. 616–625 (October 1995)

    Google Scholar 

  17. Zhang, Y., Agrawal, V.D.: An Algorithm for Diagnostic Fault Simulation. In: Proc. 11th Latin-American Test Workshop (LATW), pp. 1–5 (March 2010)

    Google Scholar 

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Alagappan, C., Agrawal, V.D. (2013). Defect Diagnosis of Digital Circuits Using Surrogate Faults. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_44

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  • DOI: https://doi.org/10.1007/978-3-642-42024-5_44

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-42023-8

  • Online ISBN: 978-3-642-42024-5

  • eBook Packages: Computer ScienceComputer Science (R0)

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