Abstract
Aggressive design practices in nanoscale era has led to an increase in the performance of circuit at the cost of reduced slack margins. Reduced margin increases the risk of path failures due to small additional delays. In this paper, an on-chip path delay measurement architecture is designed to identify paths which violates timing constraints. A new method of measuring delay based on crossovers is proposed. Simulation results show precise measurement of path delays. Maximum path delay measured by the proposed architecture is 4.3 times the maximum delay measured by Modified Vernier Delay Line (MVDL) architecture and the area is 74% less than the area of MVDL.
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References
Maymandi-Nejad, M., Sachdev, M.: A digitally programmable delay element: design and analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(5), 871–878 (2003)
Zhang, Y., Yu, H., Xu, Q.: Coda: A concurrent online delay measurement architecture for critical paths. In: 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC), January 30-Feburary 2, pp. 169–174 (2012)
Yotsuyanagi, H., Makimoto, H., Hashizume, M.: A boundary scan circuit with time-to-digital converter for delay testing. In: 2011 20th Asian Test Symposium (ATS), pp. 539–544 (November 2011)
Datta, R., Sebastine, A., Raghunathan, A., Carpenter, G., Nowka, K., Abraham, J.A.: On-chip delay measurement based response analysis for timing characterization. J. Electron. Test. 26(6), 599–619 (2010), http://dx.doi.org/10.1007/s10836-010-5188-1
Tsai, M.-C., Cheng, C.-H., Yang, C.-M.: An all-digital high-precision built-in delay time measurement circuit. In: 26th IEEE VLSI Test Symposium, VTS 2008, April 27-May 1, pp. 249–254 (2008)
Pei, S., Li, H., Li, X.: A high-precision on-chip path delay measurement architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(9), 1565–1577 (2012)
Ghosh, S., Bhunia, S., Raychowdhury, A., Roy, K.: A novel delay fault testing methodology using low-overhead built-in delay sensor. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(12), 2934–2943 (2006)
Yang, K., Cheng, K.-T., Wang, L.-C.: Trangen: a sat-based atpg for path-oriented transition faults. In: Proceedings of the ASP-DAC 2004 Asia and South Pacific, Design Automation Conference, pp. 92–97 (January 2004)
Perform the SPICE Simulation of ISCAS85 Benchmark Circuits for Research, http://www.ece.uic.edu/~masud/iscas2spice.htm
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Krishnamurthy, R., Sharma, G.K. (2013). An Area Efficient Wide Range On-Chip Delay Measurement Architecture. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_7
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DOI: https://doi.org/10.1007/978-3-642-42024-5_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-42023-8
Online ISBN: 978-3-642-42024-5
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