Abstract
Presented is a technique to obtain test patterns for controllers. This technique is integrated in parts of the hardware design process that are based on algorithmic descriptions. So it can be performed with neglectable additional costs. It moreover effectively supports design verification. However it does not guarantee the obtained test patterns to be able to detect all single stuck-at faults. But the quality of test patterns obtained using the technique in an example is significantly better than the average quality of random test patterns. So the technique is suitable for use instead of random test patterns when combined with fault simulation and test pattern generators like the D-algorithm.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J.P. Roth: “Diagnosis of Automata Failures: A Calculus and a Method”, IBM Journal Research Development, vol.10, pp.278–291, July 1966.
P. Goel: “An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits”, Proc. 1980 Fault Tolerant Computing Symposium, pp. 145-151, Oct.1980.
Kwok-Woon Lai: “Functional Testing of Digital Systems”, Proc. 20th Design Automation Conference, IEEE 1983, pp.207-213.
P. Liell: “Testerzeugung für Datenpfade aus iterativ aufgebauten Funktionsbausteinen”, Dissertation, Abt. Informatik, Universität Kaiserslautern, FRG, 1983.
S.Y.H. Su, Tonysheng Lin: “Functional Testing Techniques for Digital LSI/VLSI-Systems”, proc. 21st Design Automation Conference, IEEE 1984, pp.517-528.
S.M. Thatte J.A. Abraham: “Test Generation for Microprocessors”, IEEE Trans. on Computers, vol.C-29, pp.429–441, June 1980.
V.K. Agarwal: “Easily Testable PLA Design”, in: T.W. Williams (edt.): “VLSI-Testing”, North Holland, 1986.
N. Tredennick: “How to Flowchart for Hardware”, IEEE Computer, vol.14, pp.87–102, Dec. 1981.
B. Koenemann, J. Mucha, G. Zwiehoff: “Built-in Logic Block Observation Techniques”, Dig. International Test Conference, IEEE 1979, pp.37-41.
T.W. Williams, K.P. Parker: “Design for Testability — A Survey”, IEEE Trans. on Computers, vol.C-31, pp.2–15, Jan. 1982.
Y.H. Levendel, P.R. Menon: “Test Generation Algorithms for Computer Hardware Description Languages”, IEEE Trans. on Computers, vol.C-31, pp.577–588, July 1982.
J.H. Hopcroft, J.D. Ullman: “Introduction to Automata Theory, Languages, and Computation”, Addison-Wesley, 1979.
J.R. Duley, D.L. Dietmeyer: “A Digital System Design Language (DDL)”, IEEE Trans. on Computers, vol.C-17, pp.850–861, Sept.1968.
R. Hartenstein: “Fundamentals of Structured Hardware Design”, North Holland 1977.
W.R. Adrion, M.A. Branstad, J.C. Cherniavsky: “Validation, Verification, and Testing of Computer Software”, Computing Surveys, vol.14, June 1982.
J.P. Hayes: “Computer Architecture and Organization”, McGraw-Hill, 1978.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1987 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Reisig, R. (1987). Test Pattern Obtainment from Algorithmic Descriptions. In: Belli, F., Görke, W. (eds) Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-45628-2_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-45628-2_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-18294-8
Online ISBN: 978-3-642-45628-2
eBook Packages: Springer Book Archive