Abstract
Test generation based on high level circuit descriptions, has been proposed in the recent years, for LSI and VLSI products. However, not all aspects of the problem have been thoroughly examined. This paper describes an efficient approach, aiming to the reduction of the computation time and input assignment requirements per test pattern. Our methodology is based on a new mode for propagating the fault symptoms through high level primitives, namely the assignments free propagation, along with a number of techniques that support this mode of propagation. Another advantage of our methodology is that it can be adapted to different algorithms. First practical results demonstrate the feasibility of our approach.
on leave at CSELT-TORINO
on leave at CERN-GENEVE
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
C. Benmehrez, J.F. McDonald, “The Subscripted D-Algorithm, ATPG with Multiple Independent Control Paths”, IEEE ATPG Workshop, PP 71-80, 1983.
Eichelberger, E.B., T.W. Williams, “A Logic Design Structure for LSI Testability”, 14th Design Automation Conf., pp 462-468, June 1977.
J. Fong, “On Functional Controllability/Observability Analysis”, IEEE Int’l Test Conf., pp 170-175, Nov. 1982.
H. Fujiwara, T. Shimono, “On the Acceleration of Test Generation Algorithms”, IEEE Trans. on Computers, vol C-32, pp 1137–1144, December 1983.
H.S. Fung, J. Fong, “An Information Flow Approach to Functional Testability Measures”, Int’l Conf. Circuits and Computers, pp. 460-463, Sept. 1982.
P. Goel, B. Rosales, “Test Generation & Dynamic Compaction of Tests”, Int’l Test Conf., pp. 189-192, 1979.
P. Goel, “An implicit enumeration algorithm to generate tests for combinational logic circuits,” IEEE Trans. on Computers., vol.C-30, pp. 215–222, Mar.1981.
R. Hartenstein, R. Hauck, “KARL III user manual and language reference internal report. University of Kaiserslautern, 1986.
T. Hu, “Combinatorial Algorithms”, Addison Wesley, 1982.
M. Kawai et al, “A High Level Test Pattern Generation Algorithm”, Int’l Test Conf., pp 346-352, IEEE 1983.
K.W. Lai, “Functional Testing of Digital Systems”, Ph.D. dissertation, Carnegie Mellon Univ., Dec 1981.
Y. Levendel, P.R. Menon, “Test Generation Algorithms for Computer Hardware Description Languages”, IEEE Trans. on Computers, vol c-31, pp. 577–588, July 1982.
Y. Levendel, P.R. Menon, “The *-algorithm:Critical Traces for Functions and CHDL Constructs”, Fault Tolerant Computing Symp., pp. 90-97, 1983.
J.P. Roth, “Diagnosis of automata failures:A calculus and a method”, IBM J. Res.Develop., vol 10, pp. 278–291, July 1966.
I. Stamelos et al, “A Multi-level Test Pattern Generation and Validation Environment”, Int’l Test Conf. 1986.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1987 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Stamelos, I., Halatsis, C. (1987). Efficient Test Generation for Register Transfer Level Descriptions. In: Belli, F., Görke, W. (eds) Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-45628-2_13
Download citation
DOI: https://doi.org/10.1007/978-3-642-45628-2_13
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-18294-8
Online ISBN: 978-3-642-45628-2
eBook Packages: Springer Book Archive