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Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems pp 72–82Cite as

Fault Tolerant VLSI Processor

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Part of the book series: Informatik-Fachberichte ((INFORMATIK,volume 147))

Abstract

The paper describes the architecture of a fault tolerant processor. Within the functional core consisting of ALU (Arithmetic Logic Unit), CCU (Computer Control Unit), PCU (Program Control Unit) and I/O-Unit all single errors can be corrected. The basic principle is the application of arithmetic, biresidual coding and linear parity coding to protect the states of the processor as well as the use of opcode-signature analysis, address changing counter and current/future check symbol technique to check the changes in the states of the processor. The architecture supports the flexible employment of fault tolerance. There are four software- controlled check-levels: check of all micro operations, check of the macro operations, check of the program flow and no check at all. The redundancy caused by coding and code-checking can be utilized for a self-test of the processor. This self-test based on coded, on-chip generated test patterns runs at the normal data rate of the processor without the need of an external reference.

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Author information

Authors and Affiliations

  1. Corporate Laboratories for Information Technology, Siemens AG, Munich, Germany

    H. P. Holzapfel & K. H. Horninger

  2. Otto-Hahn-Ring 6, 8000, München 83, Germany

    H. P. Holzapfel & K. H. Horninger

Authors
  1. H. P. Holzapfel
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  2. K. H. Horninger
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Editor information

Editors and Affiliations

  1. Fachbereich 2, Hochschule Bremerhaven, Bürgermeister-Smidt-Straße 20, D-2850, Bremerhaven, Germany

    F. Belli

  2. Institut für Rechnerentwurf und Fehlertoleranz Fakultät für Informatik, Universität Karlsruhe, Postfach 6980, D-7500, Karlsruhe 1, Germany

    W. Görke

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© 1987 Springer-Verlag Berlin Heidelberg

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Holzapfel, H.P., Horninger, K.H. (1987). Fault Tolerant VLSI Processor. In: Belli, F., Görke, W. (eds) Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-45628-2_7

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  • DOI: https://doi.org/10.1007/978-3-642-45628-2_7

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-18294-8

  • Online ISBN: 978-3-642-45628-2

  • eBook Packages: Springer Book Archive

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